Syllabus
Course Overview
Projects
Schedule
Demo
FAQs
Certificate
Syllabus
- AHB Interconnect verification project used as reference design to learn UVM & OVM
- AHB Interconnect will be verified from scratch while teaching all aspects of UVM
- What is UVM? Need for a methodology?
- How UVM evolved?
- OVM, AVM, RVM, NVM, eRM
- UVM class library
- Classification of base classes in various categories
- OOP basics
- Encapsulation
- Inheritance
- Polymorphism
- Parameterized classes
- Parameterized macros
- Static properties and static methods
- Abstract classes
- Pure virtual methods
- How above aspect correlates with UVM implementation.
- UVM Class Library, Macros, Utilities
- Detailed overview of important UVM base classes, Macros and Utility classes.
- UVM TB Architecture
- Setting up a UVM based testbench for APB protocol from scratch.
- Significance of uvm_root in UVM based testbenches.
- run_test, how it starts whole TB flow.
- Command line processor
- Reporting classes
- Uvm_report_object
- Uvm_report_handler
- Uvm_report_server
- Detailed examples on use of methods in these classes.
- Objections
- UVM Factory
- Configuration DB, Resource DB
- Detailed usage of both data bases.
- How config_db is related to resource_db?
- Using config_db to change the testbench architecture.
- TLM1.0
- Push
- Pull
- FIFO
- Analysis
- Complex example on AHB to AXI transaction conversion.
- Simulation Phases
- UVM common phases
- Scheduled phases
- Sequences, Sequencers
- Default sequence
- p_sequencer
- m_sequencer
- Test case development
- Different styles of mapping testcase to sequence
- Using default sequence and scheduled phases
- Using sequence start method
- Different styles of mapping testcase to sequence
- Configuring TB Environment
- Advanced aspects of developing a highly configurable test bench environment.
- Concept of knobs of test case scenario generation
- Using top level parameters to control the overall TB architecture
- AHB Protocol and AHB UVC development
- Coding from scratch with detailed explanation of each aspect.
- Setting up a highly configurable UVC to meet different TB requirements.
- Different testbench component coding
- Monitor
- Coverage
- Scoreboard
- Checkers
- Assertions
- Different styles of sequence development
- `uvm_do
- Start_item and finish_item
- Using existing sequences
- Sequence library
- Creating complex test cases using sequence library
- Virtual Sequencer, Virtual sequences
- Different types of sequences used in test benches
- Reset sequence
- Power up sequence
- interrupt handling sequence
- DMA handling sequence
- FSM verification sequence
- Layered sequence development
- How to create multiple layers of sequences
- Creating complex test cases using layered sequences
- Virtual sequence library
- Creating test cases using virtual sequence library
- Synchronization classes
- uvm_barrier
- uvm_event
- Container classes
- Policy classes
- uvm_printer
- uvm_recorder
- uvm_packer
- uvm_comparer
- Comparators
- In order comparator
- Algorithmic comparator
- TLM2.0
- Blocking transport
- Non-blocking transport
- Register Layer development for USB2.0 core
- Note: Doesn’t involve USB2.0 core verification
- Connecting multiple UVCs
- How to setup a complex testbench environment with multiple UVC’s connected.
- uvm_heartbeat
- How to check test bench status using heartbeat
- uvm_report_catcher
- How to handle error testcases using report catcher
- Phase jumping
- uvm_domain
- AHB Protocol
- AHB System architecture
- Features
- Signals
- Timing Diagrams
- AHB UVC Architecture
- AHB UVC Component Coding
- AHB UVC Sequence & Test Development
- AHB Interconnect Testbench Architecture
- AHB UVC & APB UVC in Interconnect Testbench setup
- Verification Component Coding
- Testcase & virtual sequence Development & Debug
- Listing down registers
- Creating Register Model
- Integrating Register Model in to Testbench
- Using Register Model to create tests
- Using Register Model in scoreboard
- UVC Development for AXI Protocol
- PCIe LTSSM FSM Verification
- Register Model Development for SPI Core
Course Overview
UVM training is a 9 weeks course provides participants with in depth exposure to all the UVM constructs using practical use case examples. Course includes 15+ assignments covering all the constructs in depth.
Course also includes multiple hands on projects based on APB, AHB test bench development. Also includes TB development for AHB interconnect model.
Projects
By working on below projects, student will get familiar with:
- AHB and APB standard protocols
- Industry standard simulation tools like Questasim & VCS
- Develop debug expertise
- UVM based TB development for complex Designs
AHB2.0 is an AMBA protocol used for medium performance applications. I was part of UVC development team. UVC was developed to work as both master and slave. Developed all the UVC components and validated UVC for various AHB features.
What student learns in this project:
What student learns in this project:
- Develop UVC Architecture to be compatible with both master and slave behavior
- List down AHB features and develop testplan for validating AHB UVC
- Develop AHB UVC components
- Integrated AHB Master UVC with slave UVC
- Develop sanity testcases and debug the same
- Develop functional tests and debug the same
APB is an AMBA protocol used for low performance applications. I was part of UVC development team. UVC was developed to work as both master and slave. Developed all the UVC components and validated UVC for various APB features.
What student learns in this project:
What student learns in this project:
- APB Protocol
- APB architecture
- Features
- Signals
- Timing Diagrams
- APB UVC Architecture
- APB UVC Component Coding
- APB UVC Sequence & Test Development
- memory Test bench development
- memory Test bench Architecture
- APB UVC integration
- TB Component Coding
- Testcase coding and debug
FIFO is a design block used for connecting components working at either same or different frequencies. This project covers all the UVM TB setup for asynchronous FIFO. This project is focused on teaching UVM constructs from practical usage perspective.
What student learns in this project:
What student learns in this project:
- Understand the functionality of Synchronous and Asynchronous FIFO
- Understand how to fix clock domain crossing issues in Asynchronous FIFO due to design working in two different clock domains, to avoid race and glitch conditions
- Develop Synchronous and Asynchronous FIFO design using Verilog
- Develop Test bench for Synchronous and Asynchronous FIFO design using Verilog
- Understand how to setup UVM TB for a design with 2 master interface
- Get hands on exposure to all UVM constructs
- Listing down features, scenarios – useful for interviews
- Develop test bench architecture using virtual sequencer
- Develop write and read interface agents
- Integrate both agents to the test bench
- Implement various test cases
- How to use virtual sequencer and virtual sequences in test case coding
- Regression setup and coverage analysis
AHB Interconnect is a configurable design used for connecting multiple AHB based masters to various AHB slaves. Design can be configured can multiple masters and multiple slaves.
What student learns in this project:
What student learns in this project:
- Develop TB Architecture to be compatible with configurable number of master and slaves
- List down design features and develop testplan
- Integrate APB UVC and AHB UVC to set up whole TB
- Configuring AHB UVC to work as a master or slave
- Develop sanity testcases and debug the same
- Develop functional tests and debug the same
- Regression setup and coverage report generation
USB2.0 core is design used for interfacing USB controller with USB2.0 based function. Design consist of multiple registers to implement endpoint and other configuration requirements. I was responsible for developing Register model for USB2.0 registers.
What student learns in this project:
What student learns in this project:
- List down registers, their fields and various attributes
- Develop register model using UVM Register layer base classes.
Schedule
| Course | UVM advanced with multiple projects – Deep dive |
|---|---|
| Duration | Live training : 9 weeks eLearning : 65 hours |
| Next Batch | |
| Schedule | |
| Freshers | 6 days/week, 4 hours/day |
| Working professionals | Saturday & Sunday(9AM – 1PM IST) Access to all course recorded videos for entire course duration |
| Tool | Questasim & VCS |
| Mode of training | Classroom training & Live online training Course can also be done in hybrid mode. |
| eLearning with dedicated mentor for doubt clarifications. | |
| Fee | Live training : INR 18K + GST eLearning : INR 15K + GST |
| Batch Size | 25 |
| Assignments | 16 |
Demo
FAQs
- Course presentations for all topics
- Session notes
- Lab documents with detailed steps
- User guides
- Expertise on SystemVerilog Language
- Exposure to Testbench coding using SystemVerilog
- Each aspect of course is supported by lot of practical examples
- AHB Interconnect is reference design from Session#1 towards implementing and learning different UVM aspects
- All UVM course examples, AHB UVC, AHB Interconnect and USB2.0 Core Verification environment implemented from scratch as part of sessions
- Dedicated full day lab sessions to ensure student does complete testbench development from scratch
Each session of course is recorded, missed session videos will be shared
- Yes, You will have option to view the recorded videos of course for the sessions missed
- You will have option to repeat the course any time in next 1 year
- Yes, Course fee also includes support for doubt clarification sessions even after course completion
- You have option to mail you queries
- Option to meet in person to clarify doubts
Certificate
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- 1-1 Dedicated Mentor Support
- 24/7 Tool Access
- Multiple MOCK Interviews
- Industry Standard Projects
- Resume Preparation