Syllabus
Course Overview
Schedule
Demo
FAQs
Trainer
Certificate
Syllabus
- Protocol overview
- On-chip protocols
- Peripheral protocols
- Limitation with on-chip protocols
- Protocol features
- PCIe protocol evolution
- PCI, PCI-X
- PCI and PCI-X overview
- PCIe topology
- PCIe Device layers
- PCIe transaction flow
- Significance of each layer
- PCIe configuration space
- Type0, Type1 header
- Capability registers
- BAR
- Enumeration
- TLP Routing
- Address routing
- ID routing
- Implicit routing
- Transaction layer
- Transaction types
- address spaces
- TLP Header fields
- TLP framing
- Virtual channel management
- Flow control
- TLP ordering rules
- TLP Prefix rules
- QOS
- Flow control
- Flow control DLLPs
- Credit types
- Data link layer
- Different DLLP types
- DLCMSM
- Flow control initialisation Protocol
- UpdateFC frequency
- Data integrity
- ACK/NAK protocol
- Physical Layer
- Physical layer Logical and Electrical sub blocks for Gen1, Gen2, Gen3 and Gen4
- Gen1, Gen2
- Special symbols
- 8b/10b encoding
- Framing
- Scrambling
- Gen3, Gen4
- Framing tokens
- Ordered sets
- TS1, TS2, EIOS, EIEOS, FTS, SKPOS
- Start of data stream OS
- Link Initialisation and Training
- LTSSM states
- Link training states
- Link parameters
- Recovery
- Speed change
- Equalization
- Low power states
- states
- Loopback, Hot reset, Disabled
- Interrupt support
- INTx Emulation
- Message signalled interrupt (MSI, MSI-X)
- Error detection and handling
- PCIe errors
- Error classification based on
- Layer
- Error classes
- Error reporting
- Error handling
- Power management
- Link power management states
- Device power management states
- ASPM
- System Reset
- Reset mechanism
- Function level reset
- PIPE
- PHY-MAC interface
- PLL, TX Block, RX Block
- PHY Interface signals
- Logic protocol analysers
- PCIe Controller verification concepts
- Testplan
- Testbench architecture
Course Overview
Course Overview
PCIe protocol training is a 6 weeks course(weekends training) focused on all the aspects of PCIe Gen1 to Gen5, including PCIe topology, configuration headers, enumeration, Transaction layer, Data link layer, Physical layer, reset, power management, interrupt handling, error handling. and PIPE.
Course also includes a dedicated session on understanding PCIe TB architecture and PCIe controller testplan etc.
Schedule
| Course | PCIe Gen4 protocol training |
|---|---|
| Duration | Live training : 6 weeks eLearning : 36 hours |
| Next Batch | |
| Schedule | Saturday, Sunday, 9AM to 12PM |
| Tool | Questasim & VCS |
| Mode of training | Live training for minimum of 10 participants or corporate training eLearning with dedicated mentor for doubt clarifications |
| Fee | Live training : INR 11K + GST eLearning : INR 9K + GST |
| Assignments | 5 |
Demo
FAQs
- Course presentations for all topics
- Session notes
- Lab documents with detailed steps
- User guides
- Exposure to standard bus protocols
- Exposure to Testbench component coding using SystemVerilog
Each session of course is recorded, missed session videos will be s
- Yes, You will have option to view the recorded videos of course for the sessions missed
- You will have option to repeat the course any time in next 1 year
- Yes, Course fee also includes support for doubt clarification sessions even after course completion
- You have option to mail you queries
- Option to meet in person to clarify doubts
Trainer
Experienced Trainer
- 12 years of work experience in Functional Verification domain across various mobile, networking, high speed peripheral domains.
- Experience of working on functional verification of Multiple Complex SOCs, multiple Sub systems
- Experience of working on multiple complex module level projects
Certificate
Play Video
- 1-1 Dedicated Mentor Support
- mock interview
- Industry Standard Projects
- Support with resume update