Syllabus
Course Overview
Schedule
Demo
FAQs
Trainer
Certificate
Syllabus
- USB2.0 protocol overview
- LS, FS, HS
- USB topology, components
- EHCI, UHCI, OHCI
- USB2.0 features
- USB reset
- Device detection
- Speed negotiation
- Enumeration
- Device descriptors
- Line states
- Data transfers
- USB core operation
- USB frame
- USB packets
- Token, Data, Handshake, Special
- New packets in high speed
- USB transfer types
- Control transfers
- Interrupt transfers
- Isochronous transfers
- Bulk transfers
- Split transactions
- USB3.2 System description
- Enhanced super speed bus architecture
- Physical Layer features
- Link layer features
- Protocol layer features
- Enhanced super speed data flow model
- Pipes
- Enhanced super speed protocol overview
- Data bursting
- IN, OUT Transfers
- Control, Bulk and Isochronous transfers
- Device notifications
- Protocol Layer
- Enhanced Super speed transactions
- Packet types
- Link management packet
- Transaction packet
- Data packet
- Isochronous Timestamp packet
- Addressing Triple
- Route String field
- Link Layer
- Byte ordering
- Link management and flow control
- Link error rules and recovery
- PowerOn Reset and Inband Reset
- Link Training and Status State Machine
- Physical Layer
- Symbol encoding
- Link initialization and training
- Clock and jitter
- Signaling
- Transmitter specifications
- Receiver specifications
- Low frequency periodic signaling
- Receiver detection
- USB3.2 Device Framework
- Power Management
- Device framework
- USB device requests
- Standard device requests
- USB protocol analyzer overview
- Basic overview of UASP, SCSI protocols
Course Overview
Course Overview
USB3.2 protocol training course is 36 hours course focused on all the aspects of USB2, USB3.0, USB3.1 and USB3.2. Course starts with fundamentals of USB protocol, then focus on LS, FS and HS aspects of USB, including all types of transfers and packets.
USB super speed and super speed plus training focus on all the aspects of USB super speed architecture including protocol layer, link layer and physical layer. Training covers all the aspects of each layers. Training also focus on PIPE.
Schedule
| Course | USB2.0 and USB3.0/3.1/3.2 Protocol training |
|---|---|
| Duration | Live training : 6 weeks eLearning : 35 hours |
| Next Batch | Live training for a minimum of 10 participants or corporate training. eLearning with dedicated mentor for doubt clarifications. |
| Schedule | Live training : Sat, Sun, 10AM to 1:30PM eLearning : recorded video access with dedicated weekend support session. |
| Mode of training | Live training eLearning |
| Fee | Live training : INR 10K + GST eLearning : INR 9K + GST |
| Assignments | 5 |
Demo
FAQs
- Course presentations for all topics
- Session notes
- Lab documents with detailed steps
- User guides
- Exposure to standard bus protocols
- Exposure to Testbench component coding using SystemVerilog
- Each session of course is recorded, missed session videos will be shared
- ption to view the rideosecorded v of course for the sessions missed
- You will have option to repeat the course any time in next 1 year
- Yes, Course fee also includes support for doubt clarification sessions even after course completion
- You have option to mail you queries
- Option to meet in person to clarify doubts
Trainer
Experienced Trainer
- 10+ years of rich experience of working in Functional Verification domain across various mobile, networking, high speed peripheral domains.
- Experience of working on functional verification of Multiple Complex SOCs, multiple Sub systems
- Experience of working on multiple complex module level projects
Certificate
Play Video
- 1-1 Dedicated Mentor Support
- Mock Interview
- Support with resume update