Hands on Synthesis tool

  1. Connect to the server:
    1.VPN login
    2.putty login
    3.VNC viwer
  2. Invoke the tool(dc_shell and icc2_shell): hands on the synthesis and physical design
    1. synthesis:
      open the synthesis tool.

In terminal :
create the dir/folder by name workshop_june
mkdir workshop_june
cd workshop_june/
mkdir PD SYNTHESIS
cd SYNTHESIS/
mkdir inputs outputs
cd inputs/

files required for the synthesis:

  1. RTL files(.v or .vdl)
  2. .lib (liberty files) –> timeing and power information of the statandcells and macros.
  3. .sdc (synopsys design constaints) –> information about the clock and timimg period.

paths to copy all the above files into inputs dir.

cp -rf /home/abhi/workshop/chiptop_gprs/syn2/inputs/rtl/ ./
cp -rf /home/abhi/workshop/chiptop_gprs/syn2/inputs/chiptop.sdc ./
cp -rf /home/vlsiguru/ORCA_TOP/ref/DBs/saed32ss0p95125c ./

cd ../

to invoke the synthesis(DC complier)

be into SYNTHESIS

1.csh
2.source /home/tools/synopsys/cshrc_synopsys
3.dc_shell

read the .lib(.db)

set search_path ./inputs

link_library

set link_library “saed32hvt_ss0p95v125c.db saed32rvt_ss0p95v125c.db saed32lvt_ss0p95v125c.db saed32sramlp_ss0p95v125c_i0p95v.db”

target_library

set target_library “saed32hvt_ss0p95v125c.db saed32rvt_ss0p95v125c.db saed32lvt_ss0p95v125c.db saed32sramlp_ss0p95v125c_i0p95v.db”

set a {./inputs/rtl/addpp32.v
./inputs/rtl/address_gen.v
./inputs/rtl/genpp32.v
./inputs/rtl/mult3232.v
./inputs/rtl/top_odyssey.v
./inputs/rtl/InstDecode.v
./inputs/rtl/cla.v
./inputs/rtl/csa.v
./inputs/rtl/gpr.v
./inputs/rtl/srff.v
./inputs/rtl/power_controller.v
./inputs/rtl/MemYHier.v
./inputs/rtl/MemXHier.v}

set a {./inputs/rtl/counter}

analyze

analyze -format verilog -top Chiptop -autoread $a

analyze -format verilog -top counter -autoread $a

elaborate

elaborate ChipTop

elaborate counter

load the sdc

source ./inputs/chiptop.sdc

Do Synthesis

compile_ultra

Write the nestlist

write_file -format verilog -hierarchy -output ./outputs/gprs_netlist.v

Analyse the report

report_power
report_area
report_timimg

Hands on Physical design

Hands on Physical design:

creating the working dir

open the teriminal

cd workshop_june
cd PD
mkdir inputs outputs logs
cd inputs

## copy the input files into the inputs dir

copy the ndm(new data model) into the inputs dir

cp -rf /home/vlsiguru/ORCA_TOP/ref/CLIBs/* ./

copy the netlist

cp -rf /home/abhi/workshop/chiptop_gprs/pd/inputs/ChipTop_netlist.v ./

copy the sdc file

cp -rf /home/abhi/workshop/chiptop_gprs/pd/inputs/chiptop.sdc ./

copy the tlu+ file

cp -rf /home/tools/libraries/tech/star_rcxt/saed32nm_1p9m_nominal.tluplus ./

invoke the icc2 shell tool

be in PD dir
1.csh
2.source /home/tools/synopsys/cshrc_synopsys
3.icc2_shell

########################## create the library(Only once at begining)

set search_path ./inputs

create the lib

create_lib -ref_libs {saed32_hvt.ndm saed32_rvt.ndm saed32_lvt.ndm saed32_sram_lp.ndm saed32_1p9m_tech.ndm} ./inputs/mydesign.nlib

save the lib

save_lib

Read the verilog netlist

read_verilog ./inputs/ChipTop_netlist.v
save_block

Read tlu+ file

set search_path ./inputs
read_parasitic_tech -tlup saed32nm_1p9m_nominal.tluplus -name cnom

set_parasitic_parameters -early_spec cnom -late_spec cnom

Read the sdc file

source ./inputs/chiptop.sdc
report_clocks

########## create the die and core area

Parametes

  1. Ultization : 0.7 (70%)
  2. side ratio : {1 1}
  3. core_offset : 5

initialize_floorplan -core_utilization 0.7 -side_ratio {1 1} -core_offset 5 -use_site_row
start_gui

save_block -as core_die_area

list_blocks

to generate the report

report_design

to clock report

report_clocks

### to get numbers of cells and macros through command

sizeof_collection [get_flat_cells]

# to get macro count

sizeof_collection [get_flat_cells -filter “is_hard_macro==true”]

# to get count of std_Cells

icc2_shell> sizeof_collection [get_flat_cells -filter “is_hard_macro == false”]

sizeof_collection [get_flat_cells -filter “is_hard_macro”]

#########port placement

ports are placed in between core area and die area

porta area just piece of metal layer

M7 an M8 we use for power planning

M5 and M6 layers are used to do port placement

ports should placed be on the tracks

set_block_pin_constraints -allowed_layers {M5 M6} -self
place_pins -ports [get_ports]

veriy port placement

check_pin_placement -ports [get_ports] -wire_track true

save block

save_block -as port_placement_done

#########b Macro Placement

Manually did macro placement

Do align and distribute

Align :distance between core area and macros

Distribute means : Distance between macro to macro

Apply keepout margin around macro

keepout margin : it is fence around macro where placement of std_cell is restricted

create_keepout_margin -outer {2 2 2 2} [get_flat_cells -filter “is_hard_macro”]

Fix macros

set_fixed_objects [get_flat_cells -filter “is_hard_macro”]

back to physical status placed

set_fixed_objects [get_flat_cells -filter “is_hard_macro”] -unfix

Apply soft blockage inside a macro channel

soft_blockage :Allow only inverters and buffers to be placed inside macro channel

derive_placement_blockages

save block

save_block -as macro_placement_done

open the libraray

open_lib ./inputs/mydesign.nlib

list the blocks

list_blocks

# open the block ##########3

open_block
ex: open_block macro_placement_done

#### power planning

power plan team will provide this file

based on the factors like, IR drop , all the vdd and vss to the cells and macros.

copy the power plan file

cp -rf /home/abhi/feb_workshop/PD/inputs/powerplan.tcl ./

source the file

source ./inputs/powerplan.tcl

save the power plan block

save_block -as power_plan_done

check the connectivity : M8 M7 M6 -M1

check_pg_connectivity -check_std_cell_pins none

############# Placement of cells ###########################

1. enable the coarse placement without scandef

scandef: scandef scan chain information given by DFT team

set_app_options -name place.coarse.continue_on_missing_scandef -value true

2. Enable Tie cells from the libraray

Tie cells: Tie cells produces constant logic 0 and constant logic 1.

If input of the cells should connect to logic 0 or logic 1 then connect to tie cells.

set_attribute [get_lib_cells TIE] dont_touch false
set_attribute [get_lib_cells TIE] dont_use false

3. coarse palcement

coarse placement : rough placement

create_plavement

4. legalize palcement

legalize placement means that place cells legally on the site rows

legalize_placement

5. placement optimization (STA – setup analaysis)

## Improve the placement to have less timimg violations
    # 1) reduce the congestion
    # 2) reduce timimg voilation
    # 3) reduce the power consumption

place_opt

verify voilation

report_golbal_timimg
check_pg_connectivity -check_std_cell_pins none

# save_block

save_block -as place_opt_done

################ CTS(clock tree synthesis)

CTS : meet clock transition by building clock tree using inverters and buffers

with less max latency

with less global skew

set_clock_tree_options -target_skew 0.05 -target_latency 0.4
set_max_transition 0.1 -clock_path [get_clocks]
set_lib_cell_purpose -include cts “NBUFFRVT INVRVT “
clock_opt

save the block

save_block -as clock_opt_done

Report Clock QOR

report_clock_qor > ./outputs/clock_qor.txt

Check timing violations

report_global_timing

#################### Routing #############################3

set_ignored_layers -max_routing_layer M6

Global routing :Estimation of real routing

Track assignment :Tracks are assigned for global routing

detail routing :Routing is done by using metal layers

route_auto
route_opt

save the block

save_block -as route_opt_done

gui_show_man_page

Check LVS :Layout (pd layout0 v/s schematic (Netlist)

check_lvs -max_errors 0
set_ignored_layers -max_routing_layer M6
set_app_options -name route.common.net_max_layer_mode -value soft
source ./inputs/powerplan.tcl
optimize_routes
check_lvs -max_errors 0

save the block

save_block -as route_opt_done

DRC

check_routes
route_eco

write_strem file_name.gds

Course Registration