[vc_row][vc_column][vc_custom_heading text=”Online course in Systemverilog for functional verification” use_theme_fonts=”yes”][vc_tta_tabs style=”modern” active_section=”1″][vc_tta_section title=”Overview” tab_id=”1541971500613-0ec4fc59-2bfc”][vc_column_text]Online course in SystemVerilog for Functional Verification is a 12 weeks course structured to enable engineers develop their skills in full breadth of systemverilog features. VT-SVO course covers all aspects of functional verification including constrained random verification, assertion based verification and coverage driven verification. VT-SVO course has been framed to fit to every functional verification engineer requirements and also targeted for graduates aspiring to make career in VLSI Front End domain. Course approaches by teaching basic concepts to most advanced aspects of SV with relevant examples to enable easier understanding of concepts.
VT-SVO course also includes training industry standard protocols like AXI, AHB, etc, with emphasis on teaching industry standard AXI protocol and developing Verification IP for same. Course also includes 1 industry standard project. All these projects are executed from scratch with students working on complete flow starting from specification reading, feature listing down, testbench architecture creation, component coding and testcase development till verification closure using coverage and regression as verification closure criteria.
VT-SVO course also includes multiple weeks of Lab sessions to enable student put effort in doing above projects from scratch.[/vc_column_text][/vc_tta_section][vc_tta_section title=”Syllabus” tab_id=”1541971500620-de7bef0f-b03a”][vc_toggle title=”SystemVerilog for Advanced Verification”]
[/vc_toggle][vc_toggle title=”ASIC Verification Concepts”]
[/vc_toggle][vc_toggle title=”Verification IP Development”]
[/vc_toggle][vc_toggle title=”Module(IP) Level Verification Project”]
[/vc_toggle][vc_toggle title=”Course Assignments”]
[/vc_toggle][/vc_tta_section][vc_tta_section title=”Schedule” tab_id=”1541971524428-6b46e3b3-35fe”][vc_column_text]
| Course | Systemverilog for Functional Verification | |
|---|---|---|
| Duration | 12 weeks | |
| Next Batches | 21/Nov | |
| Demo Session | 21/Nov (9AM – 1PM). | |
| Course Enroll | 22/Nov | |
| Schedule | ||
| Freshers | Full week course | |
| Saturday & Sunday(8:30AM – 4:30PM India time. Monday to Friday(9:30AM to 12:30PM). Flexible lab sessions for US Students. | ||
| Weekdays sessions will be focused on course labs, assignments and interview focused sessions. | ||
| Students also get support on complete project flow during weekdays as well. | ||
| Working professionals | Saturday & Sunday(8:30AM – 4:30PM India time. Flexible timings for students attending online from US) | |
| 8:30AM – 12:30PM (Theory session offered by trainer) | ||
| 1PM – 4:30PM (Lab & tool based session guided by mentor). Students from US will get support in different time. | ||
| Students will take the weekday tests and assignments from home. | ||
| New batch starts | Every 6 Weeks | |
| Fee | INR 20000 +GST at 18% (Online Training) | |
| Tool | Questasim | |
| Mode of training | Classroom training at VLSIGuru Institute(Horamavu) | |
| Online training using live training sessions | ||
| Tool Access | Tool access at institute for 12 months from course start date | |
| Certificate | Issued based on 50% assignment completion as criteria | |
| Batch Size | 20 | |
| Assignments | 23 | |
| Admission criteria | Student need to undergo evaluation test based on basic digital and aptitude | |
| Placement support | Interview opportunity in at least 6 companies | |
| 100% job on completion of all assignments | ||
| and scoring good grade in monthly evaluation test | ||
| Trainer | 12+ Years exp in RTL design & Functional verification |
| Content | Learning Schedule(T : Course Start Date) |
|---|---|
| Systemverilog language constructs | T to T+6th week |
| AXI Protocol and AXI VIP Development | T+6 to T+7th week |
| Memory Controller Functional Verification | T+8 to T+10th week |
[/vc_column_text][/vc_tta_section][vc_tta_section title=”FAQs” tab_id=”1541971537543-694723e5-e96c”][vc_toggle title=”What are the Course Prerequisites?”]
[/vc_toggle][vc_toggle title=”Does course cover practical sessions on SystemVerilog usage?”]
[/vc_toggle][vc_toggle title=”Is it possible to cover so many things in 8 weeks?”]
[/vc_toggle][vc_toggle title=”What if I miss few sessions during course?”]Each session of course is recorded, missed session videos will be shared[/vc_toggle][vc_toggle title=”Course has started few weeks back, can I still join the course in between?”]
[/vc_toggle][vc_toggle title=”Do you offer support after course completion?”]
[/vc_toggle][/vc_tta_section][vc_tta_section title=”Course Material” tab_id=”1541971554383-81d340d2-c773″][vc_column_text]
| Systemverilog Material | Access |
|---|---|
| Course material | Shared over google drive consists of IEEE Manual-Labs & project code |
| Course page access | Get login details from Admin |
| Assignments-Checklist-Session notes | Course page |
| Labs | Shared as part of course material and also shared every week |
| Gvim install & usage | Youtube video shared as part of course guidelines |
| How to use course material | Shared as part of Course material |
| Resume update | Shared as part of Course material |
| Interview Questions | Uploaded to course page |
| Labs for every week session | sent as mail attachment at the end of every week |
[/vc_column_text][/vc_tta_section][vc_tta_section title=”Audience” tab_id=”1541971568196-9d55b526-d7f4″][vc_column_text]Target Audience:
[/vc_column_text][/vc_tta_section][vc_tta_section title=”Trainer” tab_id=”1541971578765-2d5e1f33-6419″][vc_column_text]Trainer Profile
[/vc_column_text][/vc_tta_section][vc_tta_section title=”Overview Video” tab_id=”1541971601469-acd71df4-0ddb”][vc_video link=”https://youtu.be/ampjEFWb3RA”][/vc_tta_section][/vc_tta_tabs][/vc_column][/vc_row]