Syllabus
Course Overview
Schedule
Demo
FAQs
Trainer
Certificate
Syllabus
- Generic SOC architecture
- CPU significance in SOC
- Big-little architecture
- RISC versus CISC
- Load store architecture
- ARM processor booting
- ARM architecture family – ARMv4 to ARMv9
- ARM compiler and linker
- ARMv7, ARMv8 – A, R, M profiles
- ARM licensing model
- Big-little architecture
- A53 cluster and core architecture
- ARM core architecture
- ARM Core internal components
- ARM CoreLink
- ARM CPUSS interfaces
- ARM v7, v8 architecture
- Instruction sets
- Processor modes
- User, FIQ, IRQ, SVC, MON, ABT, UND, SYS, HYP
- ARMv7 registers
- What’s new in ARMv8?
- ARMv8 registers
- ARMv8 General Purpose Registers
- ARMv8 system control registers
- AArch32, AArch64
- Moving between AArch32 and AArch64
- AArch32 -> AArch64 register mappings
- A64 Instruction Set overview
- ARMv8 Instruction categories
- Instruction mnemonics
- ARM instruction format
- Register Load and store
- Load Instructions
- Store Instructions
- Specifying the load/store address
- Register pair load/store
- System register access instructions
- Data processing Instructions
- Shift instructions
- Bit manipulation operations
- Multiplication and division instructions
- MOV instructions
- Flow Control Instructions
- Branch Instructions
- Conditional Branch instructions
- Conditional Select instructions
- Various flags
- C to ASM code conversion example
- Status register
- ARMv8: Processor State (PSTATE)
- Flag Set instructions
- Conditional instructions
- Using concept of labels
- Using the PC
- Floating point instructions
- Memory barrier and fence instructions
- DMB – Data memory barrier
- ARMv8 FP and SIMD registers
- ARMv8 FP instructions
- ARMv8 SIMD instructions
- Keil uVision
- ARM assembly programming examples
- Add array of numbers
- Factorial
- Square of array of numbers
- Reverse a number
- Print prime numbers and count
- Find largest number in array
- Find length of a string
- Reverse array elements
- Find prime numbers in a given array
- Find Quotient and remainder
- Bubble sort
- Quick sort
- ARM compiler and Linker
- ARM assembler
- Calling ASM code in C language
- ARMv8 Exception levels – EL0, EL1, EL2, EL3
- ARMv8 registers
- Restoring the processor context
- ARMv8: Program counter
- Trust zone technology
- Secure world access
- Non-Secure world access
- Switching between both modes
- Exception and Interrupt handling
- ARM exceptions
- System calls
- SVC
- AArch64 exceptions
- AArch64 Exception and interrupt handling
- Interrupt causes
- AArch64 Vector table
- Handling synchronous exceptions
- Exception Handling
- A simple exception handler
- A nested exception handler
- Changing Execution State
- Interrupt controller
- Interrupt categories
- Interrupt registers
- Interrupt handling
- Abort handler
- GIC architecture
- Interrupt categories
- Interrupt Controller
- ARM Memory model
- Address map
- ARM Memory types
- ARM speculative access
- ARM Memory region
- Memory Types: Normal
- Memory Types: Device
- Ordering of Device accesses
- Stronger to weaker memory
- Significance of memory types
- Cache basics
- ARMv8 Cache architecture
- Cache access
- Cache line and Tag
- Cache terminology
- Cache implementation styles
- Fully associative Cache
- Direct mapped Cache
- N-way set-associative Cache
- 2-way set-associative Cache example
- Cache coherency
- Coherency basics – Writes/Reads
- Cache state model
- Memory attributes
- Inclusive and exclusive caches
- Cacheability
- Access permissions
- Physical address spaces
- Cache controller
- Cache policies
- ACE Coherency
- MOESI protocol
- ACE protocol channels
- Snoop address channel
- Snoop response channel
- Snoop data channel
- Domains
- Shareable reads
- Shareable writes (Write-back caching)
- Basics of OS
- Memory management Unit
- MMU VA to PA mapping
- Translation Lookaside Buffer (TLB)
- MMU Address Translation
- Page table entry size
- 2 Level page tables
- Page fault
- LPAE
- Separation of kernel and application VA spaces
- Translating a Virtual Address to a Physical Address
- Physical address spaces
- How a physical address is formed
- MMU Enabling and disabling
- AArch64 Translation Tables
- Translation Control Register
- HW virtualization
- Hypervisor
- Why HW virtualization is required?
- How HW virtualization is used?
- Hypervisor software
- What is MPU?
- Why MPU is required?
- How MPU is used?
- Memory region attributes
- Different types of memories
- How to configure MPU
- ARM Pipelining
- 5 stage Pipelining
- Types of instruction – pipeline stages
- Pipelining in ARMv8
- Purpose of CoreSight Architecture
- Structure of the CoreSight Architecture
- JTAG
- CoreSight Trace infrastructure
- CoreSight component types
- Trace links
- Trace sinks
- Off chip trace sinks
- Debug ports and access ports
- CoreSight topology detection
- DAP
- CoreSight SOC components
- CoreSight Embedded Cross Trigger (CTI & CTM)
- CTI configuration
- Cross Triggering
- Trace sources
- ARM Power management
- Power consumption – types
- Power management techniques
- Idle management
- Standby
- Retention
- Power down
- Dormant mode
- Hotplug
- DVFS
- Assembly language power instructions
- Power state coordination interface
Course Overview
Course Overview
95%+ of portable device SOCs has at least one ARM processor inside them. This
is the importance of ARM. ARM processor is implemented in different architectures starting from ARMv4 till ARMv9. This course explores the ARMv7 and ARMv8 architecture and ISA in depth.
The ARM Architecture Training course includes ARM processor profiles, CPUSS architecture, ARMv7 and ARMv8 ISA, instruction set, FP, SIMD instructions, assembly coding examples, exception levels, Cache, Cache coherency, MMU, VA to PA translation, MPU, pipelining, coresight architecture and power management in ARM.
Schedule
| Course | ARM Architecture Training |
|---|---|
| Duration | Live training : 6 weeks eLearning : 36 hours |
| Next Batch | |
| Schedule | Saturday, Sunday, 9AM to 1PM |
| Tool | Kiel |
| Mode of training | Live training for minimum of 10 participants or corporate training. eLearning with dedicated mentor for doubt clarifications. |
| Fee | Live training : INR 14K + GST eLearning : INR 11K + GST |
Demo
FAQs
- Course presentations for all topics
- Session notes
- Lab documents with detailed steps
- User guides
- Expertise on any processor architecture, 8086, etc
- Exposure to basic assembly coding, instruction set, etc
- Each aspect of course is supported by lot of practical examples
- ARM boards used to implement the examples
Each session of course is recorded, missed session videos will be shared
- Yes, You will have option to view the recorded videos of course for the sessions missed
- You will have option to repeat the course any time in next 1 year
- Yes, Course fee also includes support for doubt clarification sessions even after course completion
- You have option to mail you queries
- Option to meet in person to clarify doubts
Trainer
Experienced Trainer
- 15+ years of rich experience of working in Functional Verification domain across various mobile, networking, high speed peripheral domains.
- Experience of working on functional verification of Multiple Complex SOCs, multiple Sub systems
- Experience of working on multiple complex module level projects
Certificate
- 1-1 Dedicated Mentor Support
- mock interview
- Industry Standard Projects
- Support with resume update