Home
Courses
Freshers
Functional / ASIC verification
Physical Design
FPGA system design & verification
Design for testability (DFT)
Custom/Analog layout
Embedded systems
Working professionals
RTL design and integration
Functional verification for experienced
Physical design
Design for testability (DFT)
Custom and Analog Layout
Synthesis and STA
IR Drop analysis using RedHawk
Protocol Courses
PCIe Gen5
AMBA(AXI, AHB, and APB)
DDR1 to DDR4, LPDDR1 to LPDDR4
DDR5
AMBA CHI Training
USB2.0 & USB3.x
USB4
SPI, I2C and UART
ACE protocol
Display Port
NVMe
CXL Training
Short Term Courses
Verilog
System Verilog
UVM Course
UVM advanced course with multiple projects
Systemverilog assertions and coverage
UVM Register model training
LEC formal
Lint and CDC
Formal property verification
Advanced digital design
VHDL
SoC
SOC Design & Verification
Functional verification debug techniques
ARM v8 architecture
UPF power aware verification
RISC-V ISA
Gate level simulations(GLS)
Scripting
PERL training
Python training
TCL scripting training
Linux training
GVIM training
Shell scripting training
Interview preparation courses
Functional Verification interview preparation
Physical Design interview preparation
DFT interview preparation
Embedded system interview preparation
FPGA interview preparation
Functional verification projects
DMA Controller verification using SV & UVM
Ethernet MAC verification using SV & UVM
USB2.0 Core verification using SV & UVM
AXI2OCP bridge verification using SV & UVM
Universal Memory Controller verification using SV & UVM
BTech & MTech Internship
MTech VLSI Projects & Internship
MTech Embedded systems projects & internship
VLSI short term internship
Embedded systems summer internship
Schedule
E-Learning
1-1 Training
Placements
Corporate Training
Contact
Home
Courses
Freshers
Functional / ASIC verification
Physical Design
FPGA system design
Design for testability (DFT)
Custom/Analog layout
Embedded systems
Working professionals
RTL design and integration
Functional verification
Physical Design
Design for testability (DFT)
Custom and Analog Layout
Synthesis and STA
IR Drop analysis using RedHawk
Protocol Courses
PCIe Gen5
AMBA(AXI, AHB, and APB)
DDR to DDR4, LPDDR to LPDDR4
DDR5
SPI, I2C and UART
AMBA CHI Training
USB2.0 & USB3.x
USB4
ACE protocol
Display Port
NVMe
CXL Training
Short Term Courses
Verilog
System Verilog
UVM course
UVM advanced course with multiple projects
Advanced digital design
VHDL
Systemverilog assertions and coverage
UVM Register model training
LEC formal
Lint and CDC
Formal property verification
SoC
SOC Design & Verification
Functional verification debug techniques
ARM v8 architecture
Power Aware Verification
RISC-V ISA
Gate level Simulations(GLS)
Scripting
PERL Training
Python Training
TCL scripting training
Linux training
Gvim training
Shell Scripting training
interview preparation
FUNCTIONAL VERIFICATION interview preparation
Physical Design interview preparation
DFT interview preparation
Embedded system interview preparation
FPGA interview preparation
Projects
Functional verification projects
Universal Memory Controller
USB2.0 Core Verification
DMA Controller
Ethernet MAC
MTech Projects & Internship
MTech VLSI Intership
MTech Embedded Systems Intership
Course Schedule
E-Learning
1-1 Training
Placements
Placement Support Policy
Physical Design Placements
Functional verification placements
DFT placements
Embedded systems placements
Custom-Layout-Placements
FPGA-placements
Corporate Training
Contact Us
Home
CLOCK_TREE_SYNTHESIS(pavan)
Course Registration
