Overview of Basics of Dubbing , EM, IR.(Theory : 3 hrs) |
Average Dubbing Calculation and Static Analysis.(Theory : 3 hrs) |
IP Modelling Techniques (Theory : 3hrs) |
APL Characterisation(3hrs) |
Dynamic Analysis Vectorless Single Cycle and Multi Cycle Flows (Theory 3 hrs) |
Dynamic Vectored Analysis(3 hrs) |
Redhawk Signal EM(3hrs) |
Low Debugging Design Analysis(3 hrs) |
Setup of flow(3hrs) |
Day 1: |
Overview of Debugging skills. |
Labs: Understanding of Input files of Redhawk, Setting up of Redhawk Env. |
Day 2: |
Basics of Debugging, EM, IR. |
Data Preparation Generation of Collaterals from ICC |
Understanding Volcano Design. |
IP Modelling Techniques. |
Labs: |
Analyzing of APL using utilities Aqua and ACE. |
Sanity Checks of all Inputs Colleterals. |
Day 3: |
Grid Weakness Checks, Resistance Extraction. |
Labs: |
Performing PG Resistance Analysis – effective resistance of Instances, Pin Path Resistance Checks |
Missing Vias Checks, |
Analyzing Shorts, |
Disconnected Instances, |
Connectivity Checks. |
Day 4 & 5: |
Average Debugging Calculation, |
Static Analysis Theory, |
Redhawk Static IR/EM Flow |
Labs: |
Setting Up of GSR for Static Run. |
Creation of Command run file. |
Debugging Calculation in Static Analysis using Toggle rate. |
Debugging Calculation in Static Analysis using BPFS. |
Doing experiments with BPFS. |
Exploration of Redhawk TCL Commands for advanced Debugging of IR Drop. |
Creation of Custom lib’s for Missing PG Arcs. |
Exploration of Redhawk Explorer. |
Exploration of Debugging Maps. |
Package and PAD Constraints. |
Results Exploration and Debugging. |
Debugging EM Violations. |
Analyzing Hot spots. |
Analysis Battery Currents and Demands Currents. |
Day 6 & 7. |
Dynamic Vectorless Analysis |
Dynamic Flow |
Labs: |
Setting Up of GSR for Static Run. |
Creation of Command run file. |
Plotting Instance current |
Min, Max, Avg DVD in Timing Window and min DVD in Whole Simulation Cycle. |
Analysis of Switches and its equivalent reports |
Wire IR Drops |
Exploration of DVD Histograms. |
Plotting Instance Voltage Waveform. |
Plotting Switching Histograms. |
Analyzing Switching events |
Decap Density Maps |
Dynamic Voltage Drop Movie. |
Analysis Dynamic Reports |
Design Weakness Checks |
Pad Current Checks |
Decap Efficiency Checks |
Simultaneous Switching Checks |
Frequency Domain based Demand Current Checks |
Voltage Domain based Demand Current Checks |
Cross Probing Violations in Redhawk GUI |
Hotspot Analysis Summary |
DVD Check – Instance Level Debug |
Short Path Tracing of Instances |
Debugging EM Checks |
Day 8: |
Multicycle Vectorless Analysis |
Labs: |
Correlation between Single Cycle and Multicycle analysis |
Cycle based Switching |
All labs on Dynamic Vectorless will be applicable to Multicycle |
Running Debugging IR/EM on Volcano or ORCA_TOP |
Running Redhawk on Debugging IR/EM Ansys Design. |
Assignments |
Labs: |
Static EM/IR Analysis.(6hrs) |
Dynamic EM/IR Vectorless Analysis Single Cycle.(6hrs) |
Dynamic EM/IR Vectorless Analysis Multi Cycle.(6 hrs) |
Dynamic Vectored Analysis Worst Debugging Cycle.(6hrs) |
Dynamic Vectored Analysis Worst dpdt Cycle.(6 hrs) |
Signal EM Analysis.(3hrs) |
Low Debugging Design Analysis(6 hrs) |
Ansys training is a 8 weeks training program targeted for standard Debugging noise and reliability sign-off solution for SOC designs. RedHawk helps create high-performance SoCs which are Debugging efficient and reliable for electromigration, thermal and electrostatic discharge issues. RedHawk is the sign-off solution for all the foundries. RedHawk’s advanced Distributed Machine Processing (DMP) enables significantly higher capacity and better performance for full-chip IR/dynamic voltage drop, Debugging/signal electromigration (EM) and electrostatic discharge (ESD) analyses.
Training will focus on all the aspects Debugging integrity, and IR drop analysis.
Course | Functional verification Debug Techniques Training |
---|---|
Duration | Live training : 4 weeks eLearning : 24 hours |
Next Batch | |
Schedule | Saturday, Sunday, 10AM to 1:30PM |
Mode of Training | Live training for minimum of 10 participants or corporate training eLearning with dedicated mentor for doubt clarifications. |
Fee | Live training : INR 9,000 +GST eLearning : INR 8,000 + GST |
Trainer | 14+ years exp in RTL design & Functional verification |
Experienced Trainer