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A 8-month program covering Scan, ATPG, JTAG, and MBIST with hands-on projects using Mentor Graphics Tessent and Synopsys TetraMax tools. Learn the complete DFT flow from RTL to gate-level implementation.
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1-1 Dedicated Mentor Support
24/7 Tool Access
Multiple Mock Interviews
Industry Standard Projects
Support with Resume Update
DFT Training Overview
Course Overview
DFT (Design for Testability) Training – Summary
Duration: 8 months comprehensive program
Tools: Synopsys TetraMax tools, MentorGraphics Tessent (12 months tool access post-course with extension option)
Placement Support: Institute provides placement support till candidate gets a JOB
Training Highlights:
DFT Fundamentals
Fault models: Stuck-at, Transition Delay, and Path Delay
SoC Scan Architecture and Types of Scan Designs
ATPG DRC Debug and Simulation Debug
JTAG, MBIST (Memory Built-In Self Test), and LogicBIST techniques
Test Compression Techniques using TestKompress
Hierarchical Scan Design and DFT Diagnosis
Hands-on Training:
Work on a complex SoC design with multiple memory blocks
Apply MemoryBIST to test embedded memories
Boundary Scan used to manage MBIST controllers with fewer external pins
ATPG Pattern Generation for multiple fault models
Simulation-based validation of compressed test patterns
Assignments & Practice:
Extensive assignments for ATPG, Scan insertion, compression and JTAG
Multiple test cases and scenarios using Tessent tool
Practical exercises aligned with current industry needs
Training Delivery:
Concept-focused sessions with real-time lab practice
Delivered by experienced trainers from the DFT domain
Program Highlights:
In-depth, industry-relevant understanding of DFT methodologies
Hands-on learning with advanced fault models and scan architecture
Focus on ATPG, Scan, BIST, Compression, and Simulation Debug
Institute Info:
Offered by VLSIGuru, established in 2012
Trained over 10,000+ students
Affordable in-class training in Bangalore
Online training available for students outside Bangalore
Detailed overview:
DFT(Design for Testability) involves using SCAN, ATPG, JTAG and BIST techniques to add testability to the Hardware design. These techniques are targeted for developing and applying tests to the manufactured hardware. There tests in turn help catch manufacturing defects like stuck at 0, 1 faults, and transition delay faults etc.
DFT Training will focus on all aspects of testability flow including DFT basics, various fault types, SOC Scan Architecture, different scan types, ATPG DRC Debug, ATPG Simulation debug, and DFT diagnosis. DFT Training course will also focus on JTAG, MemoryBIST, LogicBIST, Scan and ATPG, test compression techniques and Hierarchical scan design.
As part of DFT Training, a complex design example with variety of memories spread around the design used as a reference for learning all testability. While MBIST used to test memories. Boundary scan is a requirement for designs, used to control the MBIST controllers that are created to minimize the need for having extra external pins to run the memory tests. ATPG test patterns will be created for various different fault models like stuck-at, transition delay, path delay fault models. Various TestKompress techniques will be used to compress test patterns to ensure patterns can be applied on minimal number of IO pins used during test. Compressed test patterns will run more quickly on the production test floor and require less tester memory. Patterns are validated through Simulations.
DFT Training course is designed as per the current industry requirements with multiple hands on projects based on Scan, ATPG, JTAG and MBIST. DFT Training will help student with in-depth knowledge of all testability techniques. Hands-on project will involve creating large number of test cases for various aspects like Scan insertion, Compression, JTAG and ATPG pattern generation using Tessent tool. More importance is given to basic concepts, interaction sessions, hands-on, important notes and assignments.
MentorGraphics Tessent tool is used for training. As per industry survey, it is used by more than 80% companies for DFT. Student will have access to tool at the institute for 12 months after course completion, with a provision to extend beyond.
Mentor Graphics Tessent and Synopsys
VLSI Design flow
- Specification
- RTL coding, lint checks
- RTL integration
- Connectivity checks
- Functional Verification
- Synthesis & STA
- Gate level simulations
- Power aware simulations
- Placement and Routing
- DFT
- Custom layout
- Post silicon validation
Digital Design - Deep dive
- Combinational logic
- Number systems
- Radix conversions
- K-maps, min-terms, max terms
- Logic gates
- Realization of logic gates using mux's and universal gates
- Compliments (1/2/9/10's complement)
- Arithmetic operations using compliments
- Boolean expression minimization, Dmorgan theorems
- POS and SOP
- Conversion and realization
- Adders
- Half adder
- Full adder
- Subtractor
- Half subtractor
- Full subtractor
- Multiplexers
- Realizing bigger Mux's using smaller Mux's
- Implementing Adders and subtractors using Multiplexers
- Decoders and Encoders
- Implementing Decoders and Encoders using Mux and Demux
- Bigger Decoder/Encoder using smaller Decoder/Encoder
- Comparators
- Implementing multi bit Comparators using 1-bit Comparator
- Sequential logic
- Latch, Flipflop
- Latch, Flipflop using Gates or Mux's
- Different types of FFs
- FF Truth table
- Excitation tables
- Realization of FF's using other FF's
- Applications of FF's, Latches
- Counters
- Shift registers
- Synchronizers for clock domain crossing
- FSM's
- Mealy, Moore FSM
- Different encoding styles
- Frequency dividers
- Frequency multiplication
- STA
- Setup time, Hold time, timing closure
- fixing setup time and hold time violations
- Launch flop, capture flop
Linux operating system
- Installing Linux platform in Windows
- Linux basics
- Linux versus Windows
- Linux Terminal
- File and Directory management
- Changing file permissions
- Absolute path and relative path
- Working with directories
- GVIM – major keyboard shortcuts
- Text display commands
- Root configuration files
- Environment variables
- Text processing commands
- grep, fgrep
- xargs
- SEd
- AWK
- Pipes and filters
- Connecting to server
- Process management
- LSF
- Ping
- FTP
- CTAGs
- File compress and extract
- Soft links
TCL Scripting
- Introduce TCL
- Why TCL?
- TCL Script Processing
- Understand TCL uses and strengths
- Writing simple TCL scripts
- TCL for VLSI scripting
- TCL: Main Features
- TCL in EDA
- TCL shell (tclsh)
- Working with TCL scripts (UNIX)
- TCL Interpreter in SoC Design Tools
- TCL Scripting for SoC Design
- TCL Commands
- Variables
- Substitution and Command Evaluation
- Operators
- Mathematical Functions
- Procedures
- Control flow: if, if-else, switch, for, foreach, while, break and continue string, string operations
- List, List manipulation
- Arrays, array methods
- Working with files
- Command line arguments
- Regular expressions
- Complete TCL Scripts
- TCL Packages
Verilog basics
- Verilog language constructs
- Combinational logic implementation using Verilog
- Testbench coding for combinational logic
- Sequential logic implementation using Verilog
- Testbench coding for sequential logic
- Clock generation with frequency, Jitter and duty cycle
- Memory coding and test bench setup
- Running simulations, analysing waveforms, debugging concepts
Design For Testability (Below is DFT Main course weekly schedule)
- DFT Basics
- SoC Scan architecture overview
- Types of Scan
- ATPG DRC Debug
- ATPG Simulation Mismatch Debug
- DFT Diagnosis
- JTAG
- MemoryBIST
- LogicBIST
- Scan and ATPG
- Test compression techniques
- Hierarchical Scan Design
Week-1
- Introduction to DFT
- Roles in DFT
- Full SOC flow - DFT
- DFT Architecture and Basics
- Test Plan
- Different DFT schemes
- Comparison between Functional and DFT Vectors
- Defect, Fault and Error
- Revision of Digital Concepts
Week-2
- Understanding of SCAN Insertion
- Scan methodology
- Types of Scan
- Top-down and Bottom-up Approach
- Scan insertion Flow
- Scan operation
- Clocking structure relation in SCAN
- DFT rule checks - Clock and Reset
Week-3
- Scan insertion Scripts
- Multiple Clock domains
- DFT Rule Checks - Advanced (Tristate, PRC, XS)
- Precautions for building a proper scan chain
- Edge and Domain Mixing significance
- Scan Configurations
- Scan chain Balancing
- Lock up and Terminal lockup latches
- Hands-on Scan insertion
- Explanation about Netlist and Library files
- Assignments
Week-4
- Hook-Up Scan sub chains
- Introduction to compression
- Compression Architecture
- Decompressor and Compactor
- LFSR
- Compression Ratio
- Masking Logic
- One hot Decoder
- Internal scan chains
- DRC Analysis
- Scan Reorder
- Control signals
Week-5
- Modular Compression
- Introduction to Synthesis
- Hands-on Compression
- Assignments
- ATPG Tools Introduction
- Fault Models
- Fault Categories
- Algorithms used in ATPG
Week-6
- ATPG Flow
- Coverage Analysis
- Fault Classes
- ATPG DRC's
- Hands-on Stuck-at ATPG
- Assignments
Week-7
- Concepts related to STA - Basics
- MCP and FP
- Reports of ATPG
- Sequential Depth
- Transition delay faults (TDF)
- Path delay faults (PDF)
- Hands-on TDF ATPG
Week-8
- Types of patterns
- Formats of patterns
- Fault grading
- LOC, LOS and LOES
- On chip clock control
- Advantages
- Dis-advantages
- Internal structure
Week-9
- Introduction to Validation
- Simulations flow
- Tools for simulation
- Simulation mismatches debug
- No timing and Timing based Simulations
- Hands-on Simulations
Week-10
- Flat Models
- Introduction to JTAG/IJTAG
- Introductions to PADS
- BS Insertion
- JTAG/IJTAG FSM
- Instructions of JTAG/IJTAG
Week-11
- Introduction to MBIST
- Memory faults
- Memory grouping
- Memory basics
- Algorithms
- Zero-one, CHBK, MATS, MARCH, SMARCH .etc
- MBIST Insertion on RTL
- Hands on BIST insertion
- Assignments
Week-12
- Discussion of Interview questions
- Compactor explanation
- Memory pipelining
- ET flow
- Hierarchical BIST insertion
- Hands of multi core MBIST insertion
- Assignments
Week-13
- Complete Flow of BIST insertion and validation
- Clock Monitoring
- ICL network
- EDT and OCC insertion on RTL
- Gray box generation
- Assignments
Week-14
- Introduction to ICL and PDL
- Scan Wrapper insertion - Hierarchical Flow
- Intest and Extest Hands on Lab sessions
- Assignments
- ATPG Flow with TSDB
- Faults merging
Week-15
- Controlling PLL and CLK Gen's using ICL and PDL
- Introduction to BISR
- Auxiliary Pins
- Revision of JTAG/IJTAG and BIST concepts
Week-16
- Support for Mock interviews
- Interactive sessions
- Complete Revision of DFT as follows:
- DFT Overview
- SCAN
- COMPRESSION
- OCC
- JTAG/IJTAG
- MBIST/MBISR
- ATPG
- SIMULATIONS – ATPG and BIST
- Handling third party IP's for DFT
- DFT Insertions in both RTL and NETLIST
- Total 4 levels of Projects in the entire course duration. Each Level contains 5-10 Working Labs.
Key Features
Who All Can Attend This DFT Training?
This training is ideal for professionals aiming to specialize in testability design techniques for VLSI and SoC development. It is suitable for both working engineers and fresh graduates looking to build careers in semiconductor testing and design.Pre-requisites To Take DFT Training
- There are no prerequisites for DFT training, however, having a basic understanding of Digital logic and VLSI design flow is an added advantage.
High Demand for DFT Training
Know about the Growing VLSI industry
DFT Engineers are highly valued in semiconductor companies for optimizing test coverage and reducing silicon defects. Salaries grow significantly with expertise in scan insertion, ATPG, MBIST, and experience using tools like Synopsys DFT Compiler and Tessent. Bangalore, Hyderabad, and Noida offer the highest compensation.
₹8 LPA
₹12 LPA
₹16 LPA
₹20 LPA
₹25 LPA
- Customized training programs for teams
- Upskill and reskill employees with industry-relevant content
- Interactive sessions led by expert trainers
- Hands-on projects and real-world case studies
- Flexible delivery in online
- Improve productivity and efficiency
- Access to training resources and material
- Learn in real-time with instructor-led sessions
- Flexible access from anywhere
- Recorded sessions available for revision
- Training on industry-standard tools
- Get certification after completion
- Self-paced learning as per your flexibility
- Industry-aligned learning modules
- Certification after course completion
- Access to structured video lessons and materials
- Track your progress step by step
- Access to learning materials for more than 1.5 years
DFT Training is crucial for ensuring manufactured hardware functions correctly by detecting defects like stuck-at and transition delay faults using SCAN, ATPG, JTAG, and BIST. It equips you with industry-demanded skills in testability flows, fault modeling, and test compression techniques. Mastering DFT, especially with tools like Tessent (used by 80% of companies), significantly enhances employability in the VLSI domain.
Career Path
Learning Path
At VLSIGuru, we believe that education should lead to meaningful employment. Our training programs are designed not just to impart technical excellence, but also to bridge the gap between academic learning and industry demands. With a strong network of hiring partners and a proven track record, we ensure that our students are career-ready.
Placement Highlights
- Industry-aligned curriculum
- Hands-on projects and case studies
- Communication skills
- Resume building and interview preparation
- Technical and HR mock sessions
- Aptitude and domain-specific test series
- Regular drives and exclusive hiring events with partner companies
- Resume building and interview preparation
At VLSIGURU, we provide industry-focused VLSI training and guidance that helps students and professionals build strong technical skills and succeed in their careers. Our programs are designed to be practical, flexible, and aligned with current industry requirements.
Student Reviews
Frequently Asked Questions
- Course presentations for all topics
- Session notes
- Lab documents with detailed steps
- User guides
Course does not have any pre-requisites. However any exposure to Digital design, VLSI design flow is an added advantage.
- Each session of course is recorded, missed session videos will be shared
- Yes, You will have option to view the recorded videos of course for the sessions missed
- You will have option to repeat the course any time in next 1 year
- Yes, Course fee also includes support for doubt clarification sessions even after course completion
- You have option to mail you queries
- Option to meet in person to clarify doubts
A DFT course online typically covers the fundamental concepts and techniques of Design for Testability. This includes topics like scan chain insertion, Automatic Test Pattern Generation (ATPG), Built-In Self-Test (BIST) for memory and logic, fault modeling, test compression, and various DFT architectures.
A comprehensive DFT online course usually includes video lectures, course presentations, session notes, detailed lab documents with step-by-step instructions, user guides for tools, assignments, and potentially projects. Some courses also offer doubt clarification sessions and support after completion.
A Design for Testability (DFT) course teaches the methodologies and techniques used in integrated circuit (IC) design to make the chips easier to test after manufacturing. This is crucial for identifying defects and ensuring the quality and reliability of VLSI products.
In a DFT online course, you will learn how to implement various DFT techniques into digital designs. This includes inserting scan chains, generating test patterns for different fault models, designing BIST architectures, understanding test compression methods, and analyzing test coverage.
DFT online training generally includes theoretical explanations of DFT concepts, practical hands-on exercises using industry-standard tools, and guidance on applying these techniques to VLSI designs. It may also involve assessments and support for doubt resolution.
Common topics covered in DFT training courses include:
- Introduction to DFT and its importance
- Fault models (e.g., stuck-at, transition delay)
- Scan chain architecture and insertion
- Automatic Test Pattern Generation (ATPG)
- Test compression techniques
- Built-In Self-Test (BIST) for memory (MBIST) and logic (LBIST)
- Boundary Scan (JTAG)
- DFT validation and simulation
- DFT diagnosis
A VLSI DFT course online covers the same fundamental DFT concepts and techniques but with a strong emphasis on their application and integration within the broader VLSI design and manufacturing process. It addresses the specific challenges and considerations for testing complex integrated circuits.
The VLSI DFT course at VLSIGuru is a specialized training program designed to equip individuals with the knowledge and skills required to implement Design for Testability techniques in VLSI designs, making them easier and more efficient to test after manufacturing.
A blended DFT course at VLSIGuru likely combines online learning resources (lectures, materials, virtual labs) with some in-person sessions (for hands-on labs, doubt clarification, or interactive discussions). An offline DFT course would be conducted entirely in a physical classroom setting.
The duration of the VLSI DFT course at VLSIGuru is about 7 months, depending on the depth and intensity of the curriculum.
VLSI Guru's trainers are likely experienced professionals from the VLSI industry with significant years of experience, holding relevant roles, and possessing strong technical and communication skills. Contact us to know more about this.
The DFT (Design for Testability) course extensively uses industry-standard tools to provide hands-on experience. The primary tools include Synopsys TetraMax for ATPG (Automatic Test Pattern Generation) and MentorGraphics Tessent for scan insertion, MBIST, and other advanced DFT methodologies. These tools are widely used across semiconductor companies, ensuring learners gain practical skills aligned with real-world industry practices.
VLSI Guru offer projects that simulate real-world industry scenarios to provide practical experience. These projects would likely be designed to offer hands-on learning in DFT concepts and tools.
