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Home
Courses
Freshers
Functional / ASIC verification
Physical Design
FPGA system design
Design for testability (DFT)
Custom/Analog layout
Embedded systems
Working professionals
RTL design and integration
Functional verification
Physical Design
Design for testability (DFT)
Custom and Analog Layout
Synthesis and STA
IR Drop analysis using RedHawk
Protocol Courses
PCIe Gen5
AMBA(AXI, AHB, and APB)
DDR to DDR4, LPDDR to LPDDR4
DDR5
SPI, I2C and UART
AMBA CHI Training
USB2.0 & USB3.x
USB4
ACE protocol
Display Port
NVMe
CXL Training
Short Term Courses
Verilog
System Verilog
UVM course
UVM advanced course with multiple projects
Advanced digital design
VHDL
Systemverilog assertions and coverage
UVM Register model training
LEC formal
Lint and CDC
Formal property verification
SoC
SOC Design & Verification
Functional verification debug techniques
ARM v8 architecture
Power Aware Verification
RISC-V ISA
Gate level Simulations(GLS)
Scripting
PERL Training
Python Training
TCL scripting training
Linux training
Gvim training
Shell Scripting training
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formal verification
1-1 training Highlights
10 hours of 1-1 training at student flexible timings
Support with office work debug (for working professionals)
Complete guided project support, and 24x7 tool access for hands on practice
Course content can be customized(topics added and removed) as per student requirements
Trainer support outside teaching hours.
Regular mock interviews and assessment tests for performance tracking
Course content - Hourly breakup
Formal verification (10 hours)
Topic
Duration(Hours)
Formal verification basics
1
SVA for property checking
2
Apply property checking in formal verification
2
Different formal verification use models of Formal Apps
2
Formal verification hands on project
3
Total
10
Course Registration