• Specification
• RTL coding, lint checks
• RTL integration
• Connectivity checks
• Functional Verification
• Synthesis & STA
• Gate level simulations
• Power aware simulations
• Placement and Routing
• DFT
• Custom layout
• Post silicon validation

• SOC Architecture overview
• SOC design concepts
• SOC verification concepts
• SOC Components
• SOC use cases
• SOC Testbench architecture
• SOC Test Case coding
• SOC verification differences with module verification

• Shells
• File and directory management
• User administration
• Environment variables
• Commonly used commands
• Shell scripting basics
• SEd and AWK
• Revision management
• Makefiles

• Verilog language constructs
• Verilog design coding examples covering more than 20 standard designs
  • www.vlsiguru.com/verilog-training/

• PAL, CPLD and FPGA basics
• FPGA Design Flow

• Internals of FPGA and CPLD
• Logic implementation
• FPGA Architectures of various FPGA vendors
• Anti-fuse and SRAMS
• Logic elements and Look-up Tables
• Dedicated multipliers
• Distributed RAM
• Shift registers
• MMCM
• Kintex
• Zynq
• Virtex Architectures

• Introduction and usage of IP cores·

• Modelsim/Icarus Verilog simulation
• Design Synthesis

• Design constraining and pin locking
  • Timing analysis
  • slack calculation
  • Data loss due to large skew
  • Maximum skew calculations with examples
  • Period constraints
  • Area and Power Constraints
• Static Timing Analysis
• FPGA programming
• Translate
• Map
• Floor plan
• Place and Route
• Post map and Post P&R simulation
• XDC constraints
• Reading and analysing reports-post synthesis
• Post map simulation
• Post P·&R simulation
• Configuring FPGAs
• FSM Extraction

• Timing Simulation using Modelsim/Icarusverilog
• Programming using JTAG

• Debugging techniques
  • Debugging using chip scope and Logic analyzers
  • Protocols on FPGA
  • High Speed SERDES
• Identification of the issues/resolving

• FPGA SDK environment
• FPGA Device selection

• PERL Interpreter
• Variables
• File management
• Subroutines
• Regular expressions
• Object oriented PERL
• PERL modules

• Facing interviews effectively
• industry work culture
• Group discussions

100+ detailed assignments covering all aspects from VLSI Flow, SOC Design, Verilog, Advanced digital design, System verilog, AXI protocol, VIP Development, RTL debug, UNIX and PERL scripting.

• Lab 1: Vivado IDE – create a simple HDL design and simulate the design using the HDL simulator available in Vivado design suite. Generate the bit stream and debug the design using Vivado Logic Analyzer.
  • FPGA simulation and generating the bit stream of combinational and sequential circuits, memories, and registers through the Vivado IDE
  • FPGA design of Synchronous and Asynchronous FIFO.
  • FPGA design of a I2C protocol
  • FPGA design of a SPI protocol
• Lab2:Vivado IP integrator. Vivado project and use IP Integrator to develop a basic embedded system for a target board.Extending the Embedded System into Programmable Logic
  • a. Adding Peripherals in Programmable Logic. Extend the hardware system by adding AXI peripherals from the IP catalog. Adding Your Own IP Peripheral
• Lab 3: Creating and Adding Your Own Custom IP.Use the Manage IP feature of Vivado to create a custom IP and extend the system with the custom peripheral.
• Lab 4: Software Development Environment. Writing Basic Software Applications. Write a basic C application to access the peripherals.
• Lab 5: Software Development and Debugging Software Debugging Using SDK.Use API to drive CPU’s timer. Perform software debugging using SDK.
• Lab 6: Debugging using Chip scope-Vivado Logic Analyzer cores insert various Vivado Logic Analyzer cores to debug/analyze system behavior.
• Lab7.Software Application Discussion about the Possible Applications using Zynq AP SOC
• Lab 8.Installing and running Linux. Installing Petalinux and Booting

• Expertise to C programming
• Exposure to Digital design basics

Course content covered in college(Btech/Mtech) curriculum is mostly theoretical and does not cover practical aspects. This course helps address that gap.

Each session of course is recorded, missed session videos will be shared

• Yes, You will have option to view the recorded videos of course for the sessions missed
• You will have option to repeat the course any time in next 1 year

• Student can continue to work from institute till he/she gets job
• Student has option to repeat the course as required
• Option to meet trainer in person to clarify doubts