Syllabus
Course Overview
Projects
Schedule
Demo
FAQs
Trainer
Certificate
Syllabus
- Specification
- RTL coding, lint checks
- RTL integration
- Connectivity checks
- Functional Verification
- Synthesis & STA
- Gate level simulations
- Power aware simulations
- Placement and Routing
- DFT
- Custom layout
- Post silicon validation
- Combinational logic
- Number systems
- Radix conversions
- K-maps, min-terms, max terms
- Logic gates
- Realization of logic gates using mux’s and universal gates
- Compliments (1/2/9/10’s complement)
- Arithmetic operations using compliments
- Boolean expression minimization, Dmorgan theorems
- POS and SOP
- Conversion and realization
- Adders
- Half adder
- Full adder
- Subtractor
- Half subtractor
- Full subtractor
- Multiplexers
- Realizing bigger Mux’s using smaller Mux’s
- Implementing Adders and subtractors using Multiplexers
- Decoders and Encoders
- Implementing Decoders and Encoders using Mux and Demux
- Bigger Decoder/Encoder using smaller Decoder/Encoder
- Comparators
- Implementing multi bit Comparators using 1-bit Comparator
- Sequential logic
- Latch, Flipflop
- Latch, Flipflop using Gates or Mux’s
- Different types of FFs
- FF Truth table
- Excitation tables
- Realization of FF’s using other FF’s
- Applications of FF’s, Latches
- Counters
- Shift registers
- Synchronizers for clock domain crossing
- FSM’s
- Mealy, Moore FSM
- Different encoding styles
- Frequency dividers
- Frequency multiplication
- STA
- Setup time, Hold time, timing closure
- fixing setup time and hold time violations
- Launch flop, capture flop
- SOC Architecture overview
- SOC design concepts
- SOC verification concepts
- SOC Components
- SOC use cases
- SOC Testbench architecture
- SOC Test Case coding
- SOC verification differences with module verification
- Installing Linux platform in Windows
- Linux basics
- Linux versus Windows
- Linux Terminal
- File and Directory management
- Changing file permissions
- Absolute path and relative path
- Working with directories
- GVIM – major keyboard shortcuts
- Text display commands
- Root configuration files
- Environment variables
- Text processing commands
- grep, fgrep
- xargs
- SEd
- AWK
- Pipes and filters
- Connecting to server
- Process management
- LSF
- Ping
- FTP
- CTAGs
- File compress and extract
- Softlinks
- Verilog language basics
- Verilog : How the language evolved?
- Verilog execution using Modelsim
- Verilog constructs
- Literals
- Data types
- Operators
- Continuous assignments
- Procedural timing controls
- task and functions
- system task and function
- modeling memories and FSM
- Parameters
- Port connections
- Procedural blocks
- Sensitivity list
- State machines
- timescale
- Verilog timing regions
- process
- Blocking and nonblocking statements
- Inferring combinational and Sequential logic
- fork join
- Race conditions
- Synthesis examples
- Inter and Intra delay statements
- Pipelining
- PLI
- compiler directives
- DFF coding using gate level, behavioral
- Counters
- Up counter
- Ring counter
- Johnson counter
- Memory design and verification
- Memory Verilog coding
- Front door access
- Back door access test case coding
- Test case coding and understanding waveforms
- FIFO – Synchronous FIFO and Asynchronous FIFO
- Synchronous FIFO
- Asynchronous FIFO
- Finite state machines
- Mealy and Moore style
- Implicit and Explicit styles of coding.
- Pattern detector – Overlapping, Non-Overlapping, Dynamic
- Overlapping
- Non-Overlapping
- Dynamic
- Traffic light controller
- APB protocol
- Interrupt controller
- SPI controller
- CRC generation
- PAL, CPLD and FPGA basics
- FPGA Design Flow
- Internals of FPGA and CPLD
- Logic implementation
- FPGA Architectures of various FPGA vendors
- Anti-fuse and SRAMS
- Logic elements and Look-up Tables
- Dedicated multipliers
- Distributed RAM
- Shift registers
- MMCM
- Kintex
- Zynq
- Virtex Architectures
- Introduction and usage of IP cores·
- Modelsim/Icarus Verilog simulation
- Design Synthesis
- Design constraining and pin locking
- Timing analysis
- slack calculation
- Data loss due to large skew
- Maximum skew calculations with examples
- Period constraints
- Area and Power Constraints
- Static Timing Analysis
- FPGA programming
- Translate
- Map
- Floor plan
- Place and Route
- Post map and Post P&R simulation
- XDC constraints
- Reading and analysing reports-post synthesis
- Post map simulation
- Post P·&R simulation
- Configuring FPGAs
- FSM Extraction
- Timing Simulation using Modelsim/Icarusverilog
- Programming using JTAG
- Debugging techniques
- Debugging using chip scope and Logic analyzers
- Protocols on FPGA
- High Speed SERDES
- Identification of the issues/resolving
- FPGA SDK environment
- FPGA Device selection
- PERL Interpreter
- Variables
- File management
- Subroutines
- Regular expressions
- Object oriented PERL
- PERL modules
- Facing interviews effectively
- industry work culture
- Group discussions
100+ detailed assignments covering all aspects from VLSI Flow, SOC Design, Verilog, Advanced digital design, System verilog, AXI protocol, VIP Development, RTL debug, UNIX and PERL scripting.
Course Overview
Course Overview
FPGA System Design training is a 6 months course provides participants with wider and deep understanding of the FPGA Architecture, Design, Timing closure flow and debugging.
FPGA System Design course is for both Design and verification engineers who want to gain expertise and hands on exposure to FPGA design, prototyping and Validation. FPGA training focuses on the subtleties of the Vivado flow and its add-on tools. By mastering the design methodologies presented in FPGA System Design course, participants will be able to close the timing of their designs faster, and also shorten the development time, and lower development costs.
Course combines insightful lectures with practical lab exercises to reinforce key concepts. FPGA training will also help experienced engineers working in other domains, planning to switch in to FPGA domain. Course provides multiple hands on project exposure to provide hands on exposure to the complete FPGA system design flow.
Course has been framed with a seamless interest to plug and play the FPGA boards. Every session is planned with good hands-on examples to enable quicker understanding. Lab sessions are planned at regular intervals. Traditional FPGA developers code in languages such as Verilog HDL and VHDL. These developers are comfortable with creating FPGAs using the software, closing timing on complicated hardware circuits and managing complicated I/O interfaces to the FPGA. Below is the quick review of the course.
- FPGA Architecture
- FPGA internals and I/0
- FPGA timing closure
- FPGA implementation by RTL mode as well as IP Mode
- FPGA debugging
- Software development kit environment
- Booting FPGA in petalinux/ubuntu
Projects
After completing this training, you will know how to:
- Utilisation of the primary 7 series FPGA architecture resources
- Project Manager to start a new project
- Identify the available Vivado IDE design flows (project based and non-project batch)
- Identify file sets (HDL, XDC, simulation)
- Analyse designs by using the cross-selection capabilities, Schematic viewer, and Hierarchical viewer.
- Synthesize and implement an HDL design
- Utilise the available synthesis and implementation reports to analyse a design (utilisation, timing, power, etc.)
- Build custom IP with the IP Library utility
- Make basic timing constraints
- Describe and analyse common STA reports
- Identify synchronous design techniques
- Describe how an FPGA is configured
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Lab 1: Vivado IDE – create a simple HDL design and simulate the design using the HDL simulator available in Vivado design suite.
Generate the bit stream and debug the design using Vivado Logic Analyzer.
- FPGA simulation and generating the bit stream of combinational and sequential circuits, memories, and registers through the Vivado IDE
- FPGA design of Synchronous and Asynchronous FIFO.
- FPGA design of a I2C protocol
- FPGA design of a SPI protocol
-
Lab2:Vivado IP integrator. Vivado project and use IP Integrator to develop a basic embedded system for a target board.Extending the Embedded
System into Programmable Logic
- a. Adding Peripherals in Programmable Logic. Extend the hardware system by adding AXI peripherals from the IP catalog. Adding Your Own IP Peripheral
- Lab 3: Creating and Adding Your Own Custom IP.Use the Manage IP feature of Vivado to create a custom IP and extend the system with the custom peripheral.
- Lab 4: Software Development Environment. Writing Basic Software Applications. Write a basic C application to access the peripherals.
- Lab 5: Software Development and Debugging Software Debugging Using SDK.Use API to drive CPU’s timer. Perform software debugging using SDK.
- Lab 6: Debugging using Chip scope-Vivado Logic Analyzer cores insert various Vivado Logic Analyzer cores to debug/analyze system behavior.
- Lab7.Software Application Discussion about the Possible Applications using Zynq AP SOC
- Lab 8.Installing and running Linux. Installing Petalinux and Booting
- ZYNQ Processor
- 667 MHz dual-core Cortex-A9 processor
- DDR3L memory controller with 8 DMA channels and 4 High Performance AXI3 Slave ports
- High-bandwidth peripheral controllers: 1G Ethernet, USB 2.0, SDIO
- Low-bandwidth peripheral controllers: SPI, UART, CAN, I2C
- Programmable from JTAG, Quad-SPI flash, and microSD card
- Programmable logic equivalent to Artix-7 FPGA
- Memory
- 1 GB DDR3L with 32-bit bus @ 1066 MHz
- 16 MB Quad-SPI Flash with factory programmed 128-bit random number and 48-bit globally unique EUI-48/64™ compatible identifier
- microSD slot
- Power
- Powered from USB or any 5V external power source
- USB and Ethernet
- Gigabit Ethernet PHY
- USB-JTAG Programming circuitry
- USB-UART bridge
- USB 2.0 OTG PHY with host and device support
- Audio and Video
- Pcam camera connector with MIPI CSI-2 support
- HDMI sink port (input) with CEC (Zybo Z7-20) and without CEC (Zybo Z7-10)
- HDMI source port (output) with CEC
- Audio codec with stereo headphone, stereo line-in, and microphone jacks
- Switches, Push-buttons, and LEDs
- 6 push-buttons (2 processor connected)
- 4 slide switches
- 5 LEDs (1 processor connected)
- 2 RGB LEDs (Zybo Z7-20) and 1 RGB LED (Zybo Z7-10)
- Expansion Connectors
- 6 Pmod ports (Zybo Z7-20) and 5 Pmod Ports (Zybo Z7-10)
- 8 Total Processor I/O
- 40 Total FPGA I/O (Zybo Z7-20) and 32 (Zybo Z7-10)
- 4 Analog capable 0-1.0V differential pairs to XADC
- 6 Pmod ports (Zybo Z7-20) and 5 Pmod Ports (Zybo Z7-10)
- Automotive applications
- Computer architecture
- Embedded Linux OS development
- Embedded processing systems
- Hardware/software co-design.
- Build and include hardware accelerators to meet bandwidth demanding applications
Schedule
| Course | FPGA Design & Verification Course | |
|---|---|---|
| Duration | 24 weeks | |
| Next Batch | 04/January | |
| Schedule | ||
| Freshers | Full week course | |
| Saturday & Sunday(8:30AM – 4:30PM India time. Monday to Friday(9AM to 1PM). Flexible lab sessions for US Students. | ||
| Weekdays sessions will be focused on course labs. | ||
| Students also get support on complete project flow during weekdays as well. | ||
| Working professionals | Saturday & Sunday(8:30AM – 4:30PM India time. Flexible timings for students attending online from US) | |
| 8:30AM – 12:30PM (Theory session offered by trainer) | ||
| 1PM – 4:30PM (Lab & tool based session guided by mentor). Students from US will get support in different time. | ||
| Students will take the weekday tests and assignments from home. | ||
| New batch starts | Every 8 Weeks | |
| Tool | Questasim, Vivado, Zed board | |
| Mode of training | Live online training | |
| Course is also offered in elearning mode for self paced learning | ||
| Tool Access | Tool access for complete course duration | |
| Assignments | 30 |
Demo
FAQs
- Course presentations for all topics
- Session notes
- Lab documents with detailed steps
- User guides
- Each aspect of course is supported by a lot of hands on exercises and lab.
- FPGA timing as well as prototyping.
- FPGA validation and debugging.
- Dedicated lab sessions with the tool as well as the hardware boards.
- Expertise to C programming
- Exposure to Digital design basics
Course content covered in college(Btech/Mtech) curriculum is mostly theoretical and does not cover practical aspects. This course helps address that gap.
Each session of course is recorded, missed session videos will be shared
- Yes, You will have option to view the recorded videos of course for the sessions missed
- You will have option to repeat the course any time in next 1 year
- Student can continue to work from institute till he/she gets job
- Student has option to repeat the course as required
- Option to meet trainer in person to clarify doubts
Trainer
- Multiple trainers with 10 years of average experience of working in Functional Verification domain across mobile, networking, high speed peripheral domains.
- Experience of working on functional verification of Multiple Complex SOCs, multiple Subsystems
- Experience of working on multiple complex module level projects
Certificate
Play Video
- 1-1 Dedicated Mentor Support
- 24/7 Tool Access
- Multiple mock interviews
- Industry Standard Projects
- Support with resume update