Syllabus
Course Overview
Schedule
Demo
FAQs
Trainer
Certificate
Syllabus
- Introduction to majorly used keywords on PD flow
- VLSI Technology concepts
- Resistance, Capacitance, Inductance
- Parasitic capacitance
- L-C-R circuit analysis
- RC circuit significance with circuit delay
- Clock distribution concepts, skew
- HBM3 Power-up and Initialization Sequence
- Controlled Power-off Sequence
- Initialization Sequence with Stable Power
- Initialization Sequence for Use of IEEE 1500 Instruction Including Lane Repairs and Channel Disable
- MR0 to MR15
- HBM3 Clocking Overview
- WDQS-to-CK Alignment Training
- HBM3 Data Bus Inversion (DBIac)
- Data Bus Inversion (DBIac)
- Internal DBIac State with Read
- Commands
- Command Truth Tables
- Row Commands
- Row No Operation (RNOP) Command
- ACTIVATE (ACT) Command
- PRECHARGE (PREpb) and PRECHARGE ALL (PREab) Commands
- Rounding Rules for Row Access Timings
- REFRESH Command (REFab)
- PER-BANK REFRESH Command (REFpb)
- Refresh Management (RFM)
- Adaptive Refresh Management (ARFM)
- Column Commands
- Column No Operation (CNOP)
- Read Command (RD, RDA)
- Write Command (WR, WRA)
- Mode Register Set (MRS) Command
- Power-Mode Commands
- Power-Down (PDE, PDX)
- Self Refresh (SRE, SRX)
- Parity
- Command/Address Parity
- Data Parity
- Clock Frequency Change Sequence
- Temperature Compensated Refresh Reporting
- Temperature Compensated Refresh Trip Points
- Catastrophic Temperature Sensor
- Interconnect Redundancy Remapping
- AWORD Remapping
- Row Command Bus – Remapping Table
- Column Command Bus – Remapping Table
- AWORD Remapping Examples
- DWORD Remapping
- DWORD Remapping Table
- DWORD Remapping Example
- AWORD Remapping
- HBM3 Loopback Test Modes
- HBM3 Polynomial Structure
- AWORD MISR Polynomial
- DWORD MISR Polynomial
- General Loopback Modes Features and Behavior
- AWORD and DWORD Write MISR Modes
- Test Method for AWORD (Write) MISR Mode
- Test Method for DWORD Write MISR Mode
- AWORD and DWORD Write Register Modes
- Test Method for AWORD (Write) Register Mode
- Test Method for DWORD Write Register Mode
- DWORD Read Register Mode
- Test Method for DWORD Read Register Mode
- DWORD LFSR Mode (Read direction)
- Test Method for DWORD LFSR Mode (Read direction)
- AWORD and DWORD Write LFSR Compare Modes
- Test method for AWORD (Write) LFSR Compare Mode
- Test Method for DWORD Write LFSR Compare mode
- HBM3 Polynomial Structure
- On-die DRAM ECC
- ECC Overview
- HBM3 On-die ECC Requirements
- DRAM Fault Isolation Requirements
- Error Check and Scrub (ECS)
- On-die ECC Transparency Protocol
- ECC Engine Test Mode
- WOSC
- WDQS Interval Oscillator
- tWDQS2DQ_I Offset due to Temperature and Voltage Variation
- DCA and DCM
- Duty Cycle Adjuster (DCA)
- Duty Cycle Monitor (DCM)
- Self Repair
- Absolute Maximum DC Rating
- Recommended DC Operating Condition
- Operating Temperature
- Leakage Current
- Capacitance
- DQ Rx Voltage and Timing
- AWORD Signaling
- CK and WDQS Input Signaling
- Midstack Signaling
- Transmit Driver Currents
- Output Timing Reference Load
- Output Voltage Level
- Output Rise and Fall Time
- Overshoot/Undershoot
- IDD and IPP Specification Parameters and Test Conditions
- IDD and IPP Specifications
- IDD6 Specification
- Signals
- MicroBump Positions
- HBM3 Stack Height
- HBM3 Bump Map
- Direct Access (DA) Test Port
- DA Test Port Lockout
- IEEE Standard 1500
- Interaction Between DA Test Port and IEEE1500 Test Access Port
- IEEE1500 Test Access Port I/O Signals
- IEEE1500 Test Access Port Functional Description
- Wrapper Data Register (WDR) Types
- Read Only (R) Wrapper Data Registers
- Write Only (W) Wrapper Data Registers
- Read and Write (R/W) Wrapper Data Registers
- WDR Reset State
- IEEE1500 Test Access Port Instruction Encodings
- Test Instructions
- BYPASS
- EXTEST_RX and EXTEST_TX
- HBM_RESET
- MBIST
- SOFT_REPAIR
- HARD_REPAIR
- DWORD_MISR
- AWORD_MISR
- CHANNEL_ID
- AWORD_MISR_CONFIG
- DEVICE_ID
- TEMPERATURE
- MODE_REGISTER_DUMP_SET
- READ_LFSR_COMPARE_STICKY
- SOFT_LANE_REPAIR and HARD_LANE_REPAIR
- CHANNEL_DISABLE
- CHANNEL TEMPERATURE
- WOSC_RUN and WOSC_COUNT
- ECS Error Log
- HS_REP_CAP
- SELF_REP and SELF_REP_RESULTS
- Interaction with Mission Mode Operation
- IEEE1500 Test Port AC Timing Parameters
- Boundary Scan
- Test Instructions
Course Overview
Course Overview
Schedule
Currently there is no live sessions planned. You may enroll for e-learning course for self paced learning, with option to join upcoming batch with no additional cost.
| Course | SoC Design & Verification |
|---|---|
| Duration | 3.5 weeks (weekend course) |
| Next Batch | Adhoc (when course has a minimum strength) |
| Demo Session | |
| Registration | |
| Schedule | |
| Course repeats | |
| Fee | |
| Tool | |
| Mode of training |
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| Certificate |
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| Batch Size | 20 |
| Assignments | 20 |
| Trainer | 12+ Years exp in RTL design & Functional verification |
Demo
FAQs
- Course presentations for all topics
- Session notes
- Lab documents with detailed steps
- User guides
- Course does not have any pre-requisites. However any exposure to Digital design, VLSI design flow is an added advantage.
- Each session of course is recorded, missed session videos will be shared
- Yes, You will have option to view the recorded videos of course for the sessions missed
- You will have option to repeat the course any time in next 1 year
- Yes, Course fee also includes support for doubt clarification sessions even after course completion
- You have option to mail you queries
- Option to meet in person to clarify doubts
Trainer
Experienced Trainer
- Multiple trainers, with experience of working on multiple SOC tape outs. All working in top-3 product companies.
Certificate
Play Video
- 1-1 Dedicated Mentor Support
- mock interview
- Industry Standard Projects
- Support with resume update