RTL Design and Integration training  is a 3.5-month program designed to provide comprehensive knowledge of RTL integration workflows, covering linting, CDC, manual and tool-based integration, UPF, SDC, synthesis, LEC, and STA. With multiple hands-on projects, this course prepares engineers to handle real-world RTL integration challenges in complex SoC environments.

The training emphasizes both manual integration and tool-driven approaches, including developing glue logic for block connectivity, running static checks, and performing synthesis and timing closure. Participants will gain practical experience with industry-standard tools such as Synopsys Spyglass (Lint and CDC), Design Compiler for synthesis, and PrimeTime for STA. These tools enable fast turnarounds in time-critical projects, where integration engineers are expected to deliver accurate design tags within tight timelines.

Key Areas Covered

• RTL integration methodology and glue logic development

• Linting (static analysis) – rules, guidelines, debugging, and best practices

• CDC (Clock Domain Crossing) checks using Synopsys Spyglass

• Unified Power Format (UPF) for multi-power domain SoCs

• SDC, synthesis, logical equivalence checking (LEC), and static timing analysis (STA)

• Tool-based integration and automation flows

Learning Outcomes

• Ability to perform end-to-end RTL integration on SoC-level projects

• Strong understanding of Lint and CDC methodologies with in-depth debugging skills

• Expertise in handling UPF for low-power design and power intent specification

• Hands-on experience with synthesis, STA, and design signoff flows

• Practical knowledge of industry-grade tools for time-critical integration tasks

By the end of the course, participants will be capable of independently managing RTL integration, ensuring connectivity, timing closure, and low-power intent verification in advanced semiconductor designs.