RTL INTERGRATION 1-1 training - VLSI Guru

RTL Intergration

1-1 training Highlights

150 hours of 1-1 training at student flexible timings
Support with office work debug (for working professionals)
Complete guided project support, and 24x7 tool access for hands on practice
Course content can be customized(topics added and removed) as per student requirements
Trainer support outside teaching hours.
Regular mock interviews and assessment tests for performance tracking

Course content - Hourly breakup

Digital Basics (8 Hours)

Topic	Duration(Hours)
Number System	2
Combinational logic	3
Sequential logic	3
Total

Unix Basics (8 Hours)

Topic	Duration(Hours)
Unix Directory commands , file comaparing commands	2
Filter and data manipulation Commands	2
File permission Commands and micellaneous Commands	2
Unix Environmental Variables	2
Total	8

Verilog Basics (12 Hours)

Topic	Duration(Hours)
Introduction to Verilog, Basic Synax, Operators	2
Combinational logic Design	4
Sequential logic Design	6
Total	12

Verilog Advanced (17.5 Hours)

Topic	Duration(Hours)
Memory	2
APB	1
Synchronous FIFO	1.5
Asynchronous FIFO	2
Interrupt Controller	3
PISO	3
SPI Controller	3
CRC generation	1
I2C protocol and controller	1
Total	17.5

LINT (6 Hours)

Topic	Duration(Hours)
Purpose of Linting	0.5
Rules in Spyglass Lint	0.5
Typical Lint Targets with Examples	3
Lint Labs	2
Total	6

Clock Domain Crossing (CDC) (11.5 Hours)

Topic	Duration(Hours)
CDC Basics	0.5
CDC Problem	0.5
Solution for CDC (Single bit crossing)	0.5
Multi-bit crossing (Binary Counter output, Burst Data, Stable data with valid signal)	2
Consolidation of control bits, Convergence in crossover path, Divergence in crossover path, Reconvergence of synchronized signals	1
Reset Synchronizer	1
CDC Schemes	1
Capturing Design Intent of CDC, Constraints Vs Waiver Based CD Methodologies	2
CDC labs (2 flop synchronizer, mux synchronizer, combo logic before synchronizer issue and multiple synchronization issue)	3
Total	11.5

UPF(Unified Power Format) for Low Power Design (5.5 Hours)

Topic	Duration(Hours)
Intoduction to Low Power	0.5
Power Intent and UPF	0.5
Power Reduction Techniques (Clock Gating, Power Gating, Multi-Voltage Design, Voltage/Frequency Shifting)	0.5
Special Cells (Isolation Cells, Level Shifter, Always-on Buffer, Retention Register, Power Switch)	0.5
UPF flow, Design/Logic Hierarchy, Navigation Commands	0.5
Power Domain Creation, Supply Network Creation, Power Switch Creation, Power State Definition	0.5
Retention, Isolation, Level Shifting Strategies	0.5
UPF labs	2
Total	5.5

Coretools for RTL integration (4 Hours)

Topic	Duration(Hours)
CoreBuilder, Core Assembler, Core Consultant	1
CoreTools Labs	3
Total	4

SDC (Synopsys Design Constraints) (2.5 Hours)

Topic	Duration(Hours)
SDC Basics	0.5
Defining Clocks, Defining Interface Timing, Defining Exceptions	2
Total	2.5

RTL Synthesis (19 Hours)

Topic	Duration(Hours)
Introduction to Synthesis	1
Data Setup for DC	1
Accessing Design and Library Objects	1
Constraints: Reg-to-Reg and I/O Timing	2
Constraints: Input Transition and Output Loading	2
Constraints: Multiple Clocks and Exceptions	2
Constraints : Complex Design Considerations	2
Post-Synthesis Output Data	2
Synthesis Labs	6
Total	19

Logic Equivalence Checks (LEC) (5 Hours)

Topic	Duration(Hours)
Basic concepts of Formal Verification and LEC	1
Input generation for LEC	1
LEC Labs	3
Total	5

Static Timing Analysis (STA) (8 Hours)

Topic	Duration(Hours)
What is STA, Need, Input and Output files of STA	1
Timing Paths, Slack	0.5
Setup/Hold analysis for Reg2Reg, In2Reg, Reg2Out, In2Out	2
Clock Gating Analysis	0.5
Recovery and Removal Timing	0.5
Data to Data Checks, Latch Timing	0.5
STA Labs	3
Total	8

Course Registration