Course Overview
Syllabus
Schedule
Certificate
Trainer
Demo
Course Overview
USB2.0 protocol training and USB core functional verification training is a 35 hours covering all the aspects USB2.0 protocol and SV & UVM functional verification starting from specification to verification closure.
Course involves 2 aspects:
- Training on USB2.0 protocol.
- USB2.0 Core functional verification using SV & UVM
- Design Architecture overview
- Feature listing down
- Verification plan & Test plan development
- Test bench Architecture
- Test bench component coding
- Test case coding & debug
- Coverage analysis
- Course also involves 4 assignments covering USB protocol and USB core verification.
Syllabus
- Verilog language basics
- Verilog : How the language evolved?
- Verilog execution using Modelsim
- Verilog constructs
- Literals
- Data types
- registers, nets
- Vectors, Array
- Operators
- Various styles of Modeling: Data Flow, Behavioral, Gate level, Switch level
- Continuous assignments
- Combinational logic coding : Half adder, full adder, multiplexer, comparator, encoder, decoder, priority encoder
- Generate
- Procedural timing controls
- task and functions
- system task and function
- modeling memories and FSM
- Parameters
- Port connections
- Procedural blocks
- Sensitivity list
- State machines
- timescale
- Verilog timing regions
- process
- Blocking and nonblocking statements
- Inferring combinational and Sequential logic
- Clock generation with Duty cycle & Jitter
- Shift register implementation
- Procedural Blocks
- fork join
- Race conditions
- Synthesis examples
- Inter and Intra delay statements
- example to showcase race condition using blocking assignments
- Pipelining
- Memories
- Structural modeling
- Verilog Programming Interface(& PLI)
- PLI
- compiler directives
- system task usage: $display, $monitor, $strobe
- PLI, VPI implementation
- Primitive implementation using table, endtable
- DFF coding using gate level, behavioral
- Counters
- Up counter
- Ring counter
- Johnson counter
- Memory RTL coding and TB development
- Memory Verilog coding
- Declaring a parameterized memory
- Front door access
- Back door access test case coding
- Implemneting task for front door and back door access
- Test case coding and understanding waveforms
- FIFO – Synchronous FIFO and Asynchronous FIFO
- Synchronous FIFO
- Asynchronous FIFO
- Finite state machines
- Mealy and Moore style
- Implicit and Explicit styles of coding.
- Pattern detector – Overlapping, Non-Overlapping, Dynamic
- Overlapping
- Non-Overlapping
- Dynamic
- Traffic light controller
- APB protocol
- Interrupt controller
- SPI controller
- CRC generation
Schedule
| Course | USB2.0 core functional verification |
|---|---|
| Duration | 6 weeks (30 hours) |
| Mode of learning | Currently available in eLearning mode(self paced learning with dedicated support sessions over weekend) |
| Tool | Questasim & VCS |
Certificate
Trainer
Sreenivas, Founder, VLSI Guru
Demo
Play Video
- 1-1 Dedicated Mentor Support
- 24/7 Tool Access
- Multiple MOCK Interviews
- Industry Standard Projects
- Resume Preparation