Verilog assignment 1

Assignment #1 – Combinational logic

Before doing the assignment questions, please get expertise with GVIM.

Half Adder
1. Ports
  1. Input: a, b (8 bit input)
  1. Output: s, co
1. Implement half adder logic using assign
1. Implement testbench to check the half adder behaviour
  1. Testbench file name: tb_ha.v
    1. Use :spl to create a new file tb_ha.v
  1. Include ha.v in tb_ha.v
  1. Declare all design inputs as reg
    1. Copy the same line as in design file, use ‘cw’ command to change input to reg.
      1. Use yy, y1 commands to copy lines from design file and use ‘p’ to paste in tb file.
  1. To switch between each file, use ‘Ctrl+w’, followed by up or down arrow
  1. Create half adder module instance
    1. Use ctlr+w and arrow to move cursor to ha.v file
    1. Go to design module definition line(line number 1)
      1. Use up or down arrow to move the cursor
    1. yy
    1. ctrl+w, arrow move to tb_ha.v
    1. ‘p’ to paste that line in tb_ha.v
      1. Go to the line below which we want to paste module definition
    1. Remove module
      1. Keep cursor on m of the module
      1. dw
  1. Drive a, b with random value
  1. Use $monitor to monitor a, b, s and co
1. Implement half adder logic in always block
  1. Always @(a or b)
    1. Anytime a or b changes, half adder should work
1. Implement half adder using logic gates
  1. Truth table, K-maps, Boolean expression, circuit, coding
  1. For a 8 bit input vectors, it’s quite complex
  1. DO it only using 1 bit half adder and tb also for 1 bit ha.
Full adder
1. Use half adder coded above to implement full adder
  1. Search how to implement full adder using half adder in google.
  1. Use ha_gate.v, 1 bit Half adder to do this.
  1. If this works, see how 8 bit FA can also be implemented.
1. Write test bench to check design behaviour

Implement 4×1 Mux using behavioural code
- Always
- Mux behaviour implemented using if else statements
  - Same can be done using case statement also.

Implement 4×1 Mux using continuous assignments, i.e. Data flow model.
- Assign Y = S1 ? (S0 ? i3 : i2) : (S0 ? i1 : i0);
  - Do not code assign inside always

4×1 Multiplexor using Kmaps
- Truth table for Mux output
  - Ideally, we need 64 entry truth table, but with proper understanding, we can do it in 4 entries.
    - Truth table:
    - i0 i1 i2 i3 s0 s1 y
    - ———————-
    - 0 0 i0 => this entry is y = ~s0~s1i0
    - Like above total 4 entries will be there.
      - All this minterms are ORed to get the final expression
- K-Maps
  - K-map is not required
  - Boolean expression
    - Show the final expression.
- Implement Boolean expression using Verilog logic gates
  - Inbuilt logic gates
  - Module ports?
    - How many inputs?
    - How many outputs?
      - Outputs declared as reg or wire.
  - Boolean expression: y= ~s0~s1i0 + s0~s1i1 + ~s0s1i2 + s0s1i3
    - OR of 4 AND gates.
    - How to implement AND gate in Verilog
- Write a testbench
  - Use $random with input variable concatenation to generate random inputs
    - {i0, i1….} = $random;
    - What does $random do?
      - Generates a 32 bit random number
    - What is { } does?
  - Repeat this for 20 times
    - Why we need do give #1 delay inside repeat?
  - Many students declaring n1, n2, n3, n4 in testbench also.
    - Which should not be done
    - Only Design inputs and outputs should be copied to testbench file, not the design internal signals.
- $monitor to display and check the outputs
  - Write $monitor with $time printed
  - Check how many times display happens
  - Why some timesteps are not displayed.
  - Understand how $display differs from $monitor
- Also add signals to the waveform and check the behaviour.

Implement 8×1 Mux using 4×1 Mux?
- Come up with 8×1 Mux diagram using 4×1 mux only (don’t use 2×1 mux)
- Instantiate 4x1mux to create 8×1 mux design Verilog code.
- This concept is called as Hierarchical modelling.
  - Using smaller modules, creating bigger modules.
- Module mux8x1
  - How many ports?
    - Inputs: 11
    - Outputs: 1
  - There won’t be any logic coding. It is all about instantiating 4×1 mux 3 times, connecting its ports.
- How to instantiate first 4×1 Mux in the design
  - Mux4x1 u1(.i0(i4), .i1(i5), .i2(i6), .i3(i7), .s0(s0), .s1(s1), .y(n1));
    - Connection by name
  - Mux4x1 u1(i4, i5, i6, i7, s0, s1, n1);
    - Connection by position
    - Ports order mux4x1 should be in same order as above

Multiplexer (8 to 1 mux)
- Implement 8 to 1 mux
- Write testbench to check design behaviour

Encoder, decoder and priority encoder
- Implement above designs
- Write testbench to check design behaviour

Encoder, decoder and priority encoder implementation using multiplexer
- Implement above designs using multiplexer
- Write testbench to check design behaviour

Implementing various gates using multiplexer
1. Implement AND, OR, NAND, NOR, XOR, XNOR using multiplexer

4×1 Multiplexor using Boolean expression
1. Write the Verilog code using above expression
1. Develop testbench and run the simulation.

Implement 1-bit half subtractor
1. Using above implement 1 bit full subtractor
1. Using above implement 3 bit full subtractor

Implement 8×1 mux using
1. 2 – 4×1 Mux
1. 1 – 2×1 Mux

Implement 1 bit comparator
1. Behavioral
1. Data flow
1. Structural

Implement 2 bit comparator
1. Behavioral
1. Data flow
1. Structural
  1. Using 1 bit comparator
Implement multi bit comparator
1. Behavioral
1. Data flow
1. Structural

THEORY QUESTIONS

How hardware differs from software?
How Verilog implements
1. Concept of time
1. Concept of structure
1. Concept of concurrent process
1. Concept of states
How Verilog language differs from C language?
Why Verilog is called as Hardware description language, not a programming language?
What does EDA stand for?
How EDA tools make the whole VLSI design process easier?