Syllabus
Overview
Projects
Schedule
Demo
FAQs
Trainer
Certificate
Syllabus
- Duration: 30 weeks (8 months)
- Phase#1 – 3 months
- Advanced Digital design
- GVIM text editor, Linux basics commands
- Verilog
- Phase#2 – 2.5 months
- System Verilog
- UVM
- Linux commands – hands on
- Soft skill training – regular weekly sessions
- Candidate gets placement support after 5.5 months of training, i.e after phase#2
- Phase#3 – 2.5 months
- AXI protocol and TB development
- Ethernet MAC core verification using SV & UVM
- Python
- ASIC flow and SOC verification concepts
- RISC-V based SV Verification project
- Combinational logic
- Number systems
- Radix conversions
- K-maps, min-terms, max terms
- Logic gates
- Realization of logic gates using mux’s and universal gates
- Compliments (1/2/9/10’s complement)
- Arithmetic operations using compliments
- Boolean expression minimization, Dmorgan theorems
- POS and SOP
- Conversion and realization
- Adders
- Half adder
- Full adder
- Subtractor
- Half subtractor
- Full subtractor
- Multiplexers
- Realizing bigger Mux’s using smaller Mux’s
- Implementing Adders and subtractors using Multiplexers
- Decoders and Encoders
- Implementing Decoders and Encoders using Mux and Demux
- Bigger Decoder/Encoder using smaller Decoder/Encoder
- Comparators
- Implementing multi bit Comparators using 1-bit Comparator
- Sequential logic
- Latch, Flipflop
- Latch, Flipflop using Gates or Mux’s
- Different types of FFs
- FF Truth table
- Excitation tables
- Realization of FF’s using other FF’s
- Applications of FF’s, Latches
- Counters
- Shift registers
- Synchronizers for clock domain crossing
- FSM’s
- Mealy, Moore FSM
- Different encoding styles
- Frequency dividers
- Frequency multiplication
- STA
- Setup time, Hold time, timing closure
- fixing setup time and hold time violations
- Launch flop, capture flop
- Verilog language basics
- Verilog : How the language evolved?
- Verilog execution using Modelsim
- Verilog constructs
- Literals
- Data types
- registers, nets
- Vectors, Array
- Operators
- Various styles of Modeling: Data Flow, Behavioral, Gate level, Switch level
- Continuous assignments
- Combinational logic coding : Half adder, full adder, multiplexer, comparator, encoder, decoder, priority encoder
- Generate
- Procedural timing controls
- task and functions
- system task and function
- modeling memories and FSM
- Parameters
- Port connections
- Procedural blocks
- Sensitivity list
- State machines
- timescale
- Verilog timing regions
- process
- Blocking and nonblocking statements
- Inferring combinational and Sequential logic
- Clock generation with Duty cycle & Jitter
- Shift register implementation
- Procedural Blocks
- fork join
- Race conditions
- Synthesis examples
- Inter and Intra delay statements
- example to showcase race condition using blocking assignments
- Pipelining
- Memories
- Structural modeling
- Verilog Programming Interface(& PLI)
- PLI
- compiler directives
- system task usage: $display, $monitor, $strobe
- PLI, VPI implementation
- Primitive implementation using table, endtable
- DFF coding using gate level, behavioral
- Counters
- Up counter
- Ring counter
- Johnson counter
- Memory RTL coding and TB development
- Memory Verilog coding
- Declaring a parameterized memory
- Front door access
- Back door access test case coding
- Implemneting task for front door and back door access
- Test case coding and understanding waveforms
- FIFO – Synchronous FIFO and Asynchronous FIFO
- Synchronous FIFO
- Asynchronous FIFO
- Finite state machines
- Mealy and Moore style
- Implicit and Explicit styles of coding.
- Pattern detector – Overlapping, Non-Overlapping, Dynamic
- Overlapping
- Non-Overlapping
- Dynamic
- Traffic light controller
- APB protocol
- Interrupt controller
- SPI controller
- CRC generation
- Functional Verification overview
- Test bench architecture
- Test bench components
- Test bench development : Modularity, Reusability
- Understanding Functional Verification flow
- System Verilog Course overview
- System Verilog language features
- Verilog for TB development
- Verilog Language constructs and shortcomings
- operators, data types
- Literals
- Operators – How things change from Verilog
- Data types – Integer based, string
- Arrays
- Arrays
- Array classification
- Packed and Unpacked Arrays
- Static and Dynamic Arrays
- Multi dimensional Arrays
- Dynamic Arrays
- Associative Arrays
- Queue
- Array of Queues in scoreboard implementation, other complex declarations
- Object Oriented Programming
- Basics of OOP – Class, Object, handle
- Class elements – Properties, methods, constraints
- Properties – 5 attributes in property declaration – rand/randc, signed, static, 2/4 state, data hiding
- Language provided and User defined methods
- Developing Ethernet frame and APB Tx class
- new constructor
- randomize, pre_randomize, post_randomize
- User defined methods – print, copy, compare, pack, unpack
- Encapsulation – Data hiding, local, protected, public
- Inheritance
- Ethernet frame generation example to learn OOP
- Polymorphism – real life usecases
- this, super
- Class forward declaration
- Multiple levels of inheritance
- Abstract class
- Parameterized classes
- Difference from Verilog parameterization
- Parameterization with inheritance – 4 combinations
- Parameterized classes for testbench development
- Static properties and methods
- Interface class
- Constant class property
- Scope resolution operator
- Nested class
- Variable scope
- Object copying – copy by handle, shallow copy, deep copy
- $cast – static and dynamic casting
- Advanced Data types
- Data types – Chandle, event, typedef, struct, union, enum
- Using struct data type for medals tally sorting example
- Typedef for defining complex data types
- Using complex data types in scoreboard development
- Fork join, Inter process synchronization
- Labeling
- Fork join – join_any, join, join_none
- Nested fork
- Labeling fork
- Process, process states
- Inter process synchronization
- IPS constructs – mailbox, event, Semaphore
- mailbox – types, methods
- events – persistant, synchronization examples
- Semaphore – synchronization examples
- Project to learn all SV language constructs
- Project – Memory TB development covering 90% of SV language constructs
- Configurable memory TB development
- Interface – Ports, internal signals, clocking block, modport
- using clocking block to fix design – TB synchronization issues
- Physical interface, virtual interface
- Using interface for design and TB connection
- Program
- Program significance
- How Program differs from Module
- Why Program is redundant?
- Scheduling semantics
- Scheduling semantics
- Task, Function
- Task, function – how they are different from Verilog
- Static & automatic task/functions
- System task and functions
- Constraints, Randomization
- Constraints format
- Constraints type – Simple, distribution, implication, if-else, iterative, variable ordering, soft, unique
- Inline constraints
- Constraints for queue randomization
- Constraints virtual nature
- Randomization
- randcase
- Randomization in class, module
- rand, randc
- Constrained random verification
- Directed verification
- Multiple hands on examples on Constraints and Randomization
- Chip select example using multiple inter related constraints
- new significance for randc
- Functional and code coverage
- Functional Coverage
- What is functional coverage?
- Need for functional coverage
- Where FC comes in functional verification flow?
- How to implement FC?
- Different types of FC?
- Integrating Functional coverage in Test bench
- functional coverage hierarchy
- Different types of coverpoints – simple, cross, transition
- Different types of bins – normal, illegal, ignore
- coverage calculation
- coverage options – auto_bin_max, weigth, at_least, goal, comment, name, per_instance, detect_overlap
- Listing down cover points for a design
- Instance coverage
- Cross coverage with intersect
- FC system task & Functions
- Coverage Driven Verification
- Coverage report analysis
- Cover groups with arguments
- Coverage filter using iff
- Functional coverage types in TB – transaction class coverage, register field coverage, scenario coverage
- Code coverage
- Generating code coverage
- Different types of code coverage – FSM, Conditional, Branch, Expression, Statement, Toggle
- Detailed understanding of code coverage types with examples
- Merging UCDBs, generating coverage reports
- Analyzing coverage report
- Coverage exclusion
- Assertions and Assertion based verification
- Need for assertions?
- Assertion based verification
- Types of assertions
- Immediate assertions
- Concurrent assertions
- Assertion format – antecedent, consequent
- Running assertions using questasim, debugging the assertions in waveform
- Assertion hierarchy – property, sequence, boolean expression
- ##, |-> and |=> operators
- Assertion examples for clock frequency check
- Assertion with local variables
- Assertions for simple timing diagrams
- Listing down and implmeneting assertions for simple designs – Async FIFO, Interrupt controller
- DPI
- Direct Programming Interface(DPI)
- import and export of functions
- Configuration libraries, Packages, XMR
- Configuration Libraries
- Incremental compilation
- Packages – defining, importing
- XMR
- Configuration libraries, Packages, XMR
- Compiler directives & Macros
- Parameterizable macros
- VCD – value change dump
- common array methods
- Callbacks – multiple use case examples
- What is UVM? Need for a methodology?
- How UVM evolved?
- OVM, AVM, RVM, NVM, eRM
- UVM class library
- Classification of base classes in various categories
- OOP basics
- Encapsulation
- Inheritance
- Polymorphism
- Parameterized classes
- Parameterized macros
- Static properties and static methods
- Abstract classes
- Pure virtual methods
- How above aspect correlates with UVM implementation.
- UVM Class Library, Macros, Utilities
- Detailed overview of important UVM base classes, Macros and Utility classes.
- UVM TB Architecture
- Setting up a UVM based testbench for APB protocol from scratch.
- Significance of uvm_root in UVM based testbenches.
- run_test, how it starts whole TB flow.
- Command line processor
- Reporting classes
- Uvm_report_object
- Uvm_report_handler
- Uvm_report_server
- Detailed examples on use of methods in these classes.
- Objections
- UVM Factory
- Configuration DB, Resource DB
- Detailed usage of both data bases.
- How config_db is related to resource_db?
- Using config_db to change the testbench architecture.
- TLM1.0
- Push
- Pull
- FIFO
- Analysis
- Complex example on AHB to AXI transaction conversion.
- Simulation Phases
- UVM common phases
- Scheduled phases
- Sequences, Sequencers
- Default sequence
- p_sequencer
- m_sequencer
- Test case development
- Different styles of mapping testcase to sequence
- Using default sequence and scheduled phases
- Using sequence start method
- Different styles of mapping testcase to sequence
- Configuring TB Environment
- Advanced aspects of developing a highly configurable test bench environment.
- Concept of knobs of test case scenario generation
- Using top level parameters to control the overall TB architecture
- Different testbench component coding
- Monitor
- Coverage
- Scoreboard
- Checkers
- Assertions
- Different styles of sequence development
- `uvm_do
- Start_item and finish_item
- Using existing sequences
- Sequence library
- Creating complex test cases using sequence library
- Virtual Sequencer, Virtual sequences
- Installing Linux platform in Windows
- Linux basics
- Linux versus Windows
- Linux Terminal
- File and Directory management
- Changing file permissions
- Absolute path and relative path
- Working with directories
- GVIM – major keyboard shortcuts
- Text display commands
- Root configuration files
- Environment variables
- Text processing commands
- grep, fgrep
- xargs
- SEd
- AWK
- Pipes and filters
- Connecting to server
- Process management
- LSF
- Ping
- FTP
- CTAGs
- File compress and extract
- Soft links
- Protocol basics
- Protocol overview
- Protocol features
- AMBA protocol overview
- AXI Protocol basics
- SOC Architecture – Significance of AXI protocol
- AXI based system architecture
- Correlating AXI with APB protocol
- Ports(signals) required for AXI protocol
- AXI Channels
- Write & Read Channels
- Handshaking using valid and ready
- Write Channel Signals – Address, Data and Response
- Read Channel Signals – Address and Data
- Timing diagrams
- How to draw the timing diagrams?
- Write Transaction Timing Diagram
- Read Transaction Timing Diagram
- AXI transaction analysis for big endian and little endian architecture
- Wrap transactions – write and read
- Narrow transfers
- Data bus and strobe relation
- Aligned and unaligned transfers
- AXI signal encoding
- Responses in AXI
- Locked and exclusive transfers
- Overlapping, out of order, interleaved txs
- Interconnect role in out of order transaction
- Significance of ID in AXI protocol
- AXI Channel handshake dependency
- Cacheable and bufferable transactions
- Protected transactions
- AXI VIP and UVC development
- Need for UVC?
- Different types of UVC’s
- UVC usage in module and SOC verification
- Where Passive UVC are used?
- UVC integration in to TB
- AXI UVC architecture
- AXI Transaction Definition
- AXI UVC coding
- AXI TB simulation and wave form analysis
- AXI UVC integration
- AXI scoreboard coding
- SoC Verification Concepts
- Module Level Verification
- Constrained Random Verification
- Coverage Driven Verification
- Directed Verification
- Assertion Based Verification
- Reading design specification
- How to read specification – understanding architecture, sub blocks, interfaces, registers
- Listing down features, scenarios
- Develop testplan
- Functional coverage point list down
- Develop Testbench architecture
- Testbench component coding and integration
- Develop sanity testcases(smoke tests)
- Bring up test bench environment using sanity testcases
- Develop rest of test bench components including monitor, coverage and scoreboard
- Register model(RAL) development and integration
- Register write-read, reset tests using front door and back door access
- Functional testcase coding using Register model
- Functional testcase debug using RTL, data flow and schematic tracing
- Setup regression using Python
- Debug regression failures
- Functional, Code and assertion coverage analysis
- Develop more functional tests for coverage improvement
- Schematic tracing
- RTL tracing
- FIxing RTL and TB syntax and logical errors
- SOC Architecture overview
- SOC verification concepts
- SOC Components
- SOC use cases
- SOC Testbench architecture
- SOC verification differences with module verification
- Specification
- RTL coding, lint checks
- RTL integration
- Connectivity checks
- Functional Verification
- Synthesis & STA
- Gate level simulations
- Power aware simulations
- Placement and Routing
- DFT
- Custom layout
- Post silicon validation
- Python Interpreter
- Variables
- File management
- Subroutines
- Regular expressions
- Object oriented Python
- Python modules
- Facing interviews effectively
- industry work culture
- Group discussions
100+ detailed assignments covering all aspects from Verilog, Advanced digital design, System verilog, UVM, AXI protocol, VIP Development, Ethernet MAC core verification, RTL debug, UNIX and PERL scripting.
Overview
The VLSI Functional Verification Course is an 8-month, industry-oriented training program designed to provide end-to-end exposure to front-end design and verification. This program bridges the gap between academic knowledge and semiconductor industry requirements, making it one of the most comprehensive VLSI training courses in India. Participants will gain hands-on expertise in ASIC design flow, digital design, verification methodologies, and automation scripting.
The course blends structured lectures with 75+ assignments, real-world case studies, and project-based learning to ensure that students become job-ready verification engineers.
Key Areas Covered
ASIC design flow and methodology
Advanced digital design: combinational, sequential logic, CDC, timing closure
CMOS fundamentals for digital/ASIC design
SoC design and verification concepts
Verilog, SystemVerilog & UVM with 200+ coding examples and protocol-based projects
Linux, revision control, and scripting for semiconductor workflows
Soft skills: interview preparation and communication
Learning Outcomes
Ability to work on RTL design, SystemVerilog testbenches, and UVM environments
Practical debugging experience using Synopsys VCS & Verdi, Mentor QuestaSim, and Cadence Xcelium
Hands-on exposure to APB, AHB, and AXI protocol projects
Confidence to handle real-world verification challenges in industry settings
This course is available in both classroom and online formats, making it accessible to students across India and abroad.
Projects
Please note, ‘VLSI Functional verification training’, ‘VLSI front end training for freshers’ and ‘VLSI design and verification training for freshers’ are all same courses and refer to the current course you are seeing.
Projects are the most significant part of any engineers(both fresher and experienced) resume. Every resume will by default have Verilog, SV and UVM. It is the projects that differentiate your resume from other resumes, which essentially helps your chances of getting through the interviews.
Below is the list of projects student will be doing as part of six months training. Student will be doing all these projects from scratch. These projects will provide student with expertise on par with a 2 to 3 years experienced engineer, in terms of all the skill set required. Student can work on additional projects to enhance resume for experienced job role.
By working on below projects, student will get familiar with:
- majority of standard protocols(AXI, AHB, APB, SPI, I2C, UART, etc)
- Industry standard simulation tools like Questasim & VCS
- Gain debug expertise
- RTL coding and TB development
- RISC-V based SV Verification project
Ethernet MAC is MAC core with transmit and receive logic working at 100Mbps. Design consists of five sub modules including DMA controller, MII, transmit, receive and control module. Course also covers the MAC 802.3 protocol standard.
This project provides student with detailed exposure to complete functional verification flow starting from reading the specification till coverage report generation and regression analysis. Student will get exposure to regression setup, coverage analysis and scoreboard development. This project is also good for working professionals whose work is generally confined to limited aspects of verification flow and want to get quick hands on exposure to complete flow.
What student learns from this project:
This project provides student with detailed exposure to complete functional verification flow starting from reading the specification till coverage report generation and regression analysis. Student will get exposure to regression setup, coverage analysis and scoreboard development. This project is also good for working professionals whose work is generally confined to limited aspects of verification flow and want to get quick hands on exposure to complete flow.
What student learns from this project:
- Understand various 802 standards and more specifically 802.3 standard
- Understand various layers in OSI reference model and significance of network layer and MAC layer.
- Understand the whole process of functional verification flow starting from Specification to coverage analysis and closure.
- Ethernet MAC Specification detailed overview
- Design specification
- Listing down features, scenarios
- Developing testplan
- Testbench architecture
- Testbench component coding
- Functional coverage coding
- Register model coding and integration
- Assertion development
- Testbench component integration
- Sanity Testcase coding
- Functional Testcase coding
- Regression setup using Python
- Regression debug
- coverage report generation and analysis
AXI3.0 is an AMBA protocol used for high performance applications. AXI3.0 supports various features like out of order transactions, burst transfers, cacheble and bufferable transactions few among various features supported.
VIP was developed to work as both master and slave. Developed all the VIP components and validated VIP for various AXI features.
What student learns from this project:
VIP was developed to work as both master and slave. Developed all the VIP components and validated VIP for various AXI features.
What student learns from this project:
- Develop VIP Architecture to be compatible with both master and slave behavior
- List down AXI features and develop testplan for validating AHB VIP
- Develop AXI VIP components
- Integrated AXI Master VIP with slave VIP
- Develop sanity testcases and debug the same
- Develop functional tests and debug the same
- Regression setup and closing of VIP validation using coverage criteria
Memory testbench was setup for configurable number of agents. Implemented the concept of semaphores to avoid the conflict from multiple agent concurrent access. Also developed reference model and checker to check memory write read behaviour. This project was done to gain practical exposure to System Verilog language constructs.
What student learns from this project:
What student learns from this project:
- Develop TB Architecture to be compatible with configurable number agent.
- List down design features and develop testplan
- Develop and integrate TB components.
- Develop sanity testcases and debug the same
- Develop functional tests and debug the same
FIFO is a design block used for connecting components working at either same or different frequencies. This project covers all the UVM TB setup for asynchronous FIFO. This project is focused on teaching UVM constructs from practical usage perspective.
What student learns in this project:
What student learns in this project:
- Understand the functionality of Synchronous and Asynchronous FIFO
- Understand how to fix clock domain crossing issues in Asynchronous FIFO due to design working in two different clock domains, to avoid race and glitch conditions
- Develop Synchronous and Asynchronous FIFO design using Verilog
- Develop Test bench for Synchronous and Asynchronous FIFO design using Verilog
- Understand how to setup UVM TB for a design with 2 master interface
- Get hands on exposure to all UVM constructs
- Listing down features, scenarios – useful for interviews
- Develop test bench architecture using virtual sequencer
- Develop write and read interface agents
- Integrate both agents to the test bench
- Implement various test cases
- How to use virtual sequencer and virtual sequences in test case coding
- Regression setup and coverage analysis
SPI Controller is design block that acts as an interface between processor and SPI slaves. SPI architecture is based on one master and multiple slaves.
SPI controller has 2 interfaces, one is APB interface used for configuring the SPI registers, address and data, other is SPI interface used for connecting with SPI slaves. SPI uses SCLK, MOSI, MISO and CS to connect master to slave.
What student learns from this project:
SPI controller has 2 interfaces, one is APB interface used for configuring the SPI registers, address and data, other is SPI interface used for connecting with SPI slaves. SPI uses SCLK, MOSI, MISO and CS to connect master to slave.
What student learns from this project:
- SPI protocol, architecture, components, signals
- SPI timing diagram – writes, reads
- SPI controller verilog coding
- SPI controller test bench development and test case coding
Interrupt is an important aspect of processor and peripheral communication in any SOC. This project focused on learning Interrupt controller verilog coding and TB development.
What student learns from this project:
What student learns from this project:
- Understand the important of Interrupt in an SOC
- Understand how the interrupt logic works in processor and peripheral communication
- Develop the Interrupt controller architecture with processor and peripheral interfacing
- Develop the Verilog code for Interrupt controller
- Learn the concept of setting up test bench for complex design
- Develop different test cases for various interrupt handling possibilities
Memory is developed using DEPTH, WIDTH and SIZE parameters to implement a configurable memory. The design and Test bench developed in Verilog language with multiple testcases. This project is focused on learning Verilog from practical use case perspective.
What student learns from this project:
- Develop memory verilog code with different parameters
- Understand memory using KB, MB, GB format. Learning calculations for Address Width calculation
- Develop TB Architecture using front door and back door access tasks
- Learn the concept of task usage in configurable test bench setup
- Learn the concept of testcases in design verification
- How to analyze the waveform for checking memory write/reads
- Develop functional tests and debug the same
PISO(Parallel In Serial Out) and SIPO (Serial In Parallel Out) are required for Serialising and De-serialising data at PHY interface. These has two interfaces for data driving from parallel interface on one side to serial interface on another side and vice versa. It collects the serial incoming data and pushes in to shift register and drives it out to upper layers as a parallel data. It collects parallel incoming data from upper layers and drives it on serial interface. Design also includes buffer to achieve non-blocking data transfers in both transmit and receive paths.
What student learns from this project:
- RTL Coding for both transmit and receive paths
- RTL integration
- Setting up Testbench and testbench component coding.
- Testplan development
- Testcase coding
CRC (Cyclic Redundancy Check) is an important concept in VLSI high speed protocols. This project is focused on learning the CRC generation logic for a bit vector using the standard CRC polynomials for CRC5, CRC16 and CRC32.
What student learns from this project:
- Understand the purpose of CRC in high speed protocols
- Understand the logic used in CRC calculation, and how it differs from binary division logic
- Develop the Verilog code for the CRC calculation
- Develop TB for CRC logic checking
Clock is important aspect of every electronic design. This project focused on understanding clock generation for a user provided frequency, duty cycle and jitter.
What student learns from this project:
- Understand the important of clock in electronic designs
- Understand how to convert frequency to time period, Hz/KHz/MHz/GHz to sec/ms/us/ns/ps
- Develop the Verilog code for clock generation using user provided frequency, duty cycle and jitter
- Learn usage of $value$plusargs for reading user arguments
- Learn usage of $value$plusargs for reading user arguments
- Develop TB for clock generation logic checking
- Understand importance of time step in clock generation logic
- RTL coding and verification of Dynamic pattern detector and overlapping & non-overlapping pattern detector
- RTL coding and verification of Dual port RAM
- Parameterizable full adder
Schedule
| Course | VLSI Frontend Training for freshers |
|---|---|
| Duration | 8 months (Placement support after 6 months of training) |
| Next Batch | 11/OCT |
| Schedule | |
| Full week course | Theory : 2.5 hours Labs : 3.5 hours every day Access to all sessions videos for revision. |
| Weekend course | Blended mode of learning Access to all the course recorded videos Saturday & Sunday. Flexible lab sessions for US Students |
| New batch starts | Every 5 Weeks |
| Tool | Synopsys (VCS, Verdi) Mentor Questasim Cadence Xcelium |
| Mode of training | Classroom training Online training Hybrid mode of training |
| Tool Access | Tool access for complete course duration |
| Assignments | 65 |
| Content | Learning Schedule(T : Course Start Date) |
| Advanced Digital Design | T to T+3rd week |
| VLSI Design Flow (ASIC flow) | T+4th week |
| Verilog for Design and Verification | T+4 to T+10 week |
| System Verilog for functional verification | T+11 to T+18th week |
| UVM for functional verification | T+19th to T+23rd week |
| Linux hands on training | T+24th week |
| Industry standard projects | T+25th to T+31st week |
| Python Scripting | T+31 to T+32nd week |
| SOC concepts, Version control | T+33rd week |
Demo
VLSI functional verification training demo video
FAQs
- Course presentations for all topics
- Session notes
- Lab documents with detailed steps
- User guides
No per-requisites. Good to know C language & exposure to Digital Design concepts
- Each aspect of course is supported by lot of practical examples
- Dedicated full day lab sessions to ensure student does complete testbench development from scratch
- Yes, You will have option to view the recorded videos of course for the sessions missed
- You will have option to repeat the course any time in next 1 year
- Yes, Course fee also includes support for doubt clarification sessions even after course completion
- You have option to mail you queries
- Option to meet in person to clarify doubts
Trainer
SrEEnivas Reddy
Senior Teacher
- Main trainer: Sreenivasa Reddy
- Founder, VLSIGuru Institute
- Dual Degree(VLSI Design), IIT Madras
- 14 years of industry experience
- 12 years training experience
- Trained around 4000+ students
- Lead Trainer for Mentor HEP 1.5 months program at Bangalore
- Corporate trainer
- Other trainers:
- 3 trainers currently working with Qualcomm and Intel.
- Experience of 10 years on average.
Certificate
Play Video
- 1-1 Dedicated Mentor Support
- 24/7 Tool Access
- Multiple mock interviews
- Industry Standard Projects
- Support with resume update