A 8-month program covering Scan, ATPG, JTAG, and MBIST with hands-on projects using Mentor Graphics Tessent and Synopsys TetraMax tools. Learn the complete DFT flow from RTL to gate-level implementation.
Next Batch
1-1 Dedicated Mentor Support
24/7 Tool Access
Multiple Mock Interviews
Industry Standard Projects
Support with Resume Update
DFT Training Overview
DFT (Design for Testability) Training – Summary
Duration: 8-month comprehensive industry-oriented program
Tools:
- Synopsys Testmax & Tetramax
- MentorGraphics Tessent
Placement Support: VLSIGuru provides dedicated placement support until every candidate secures a job in the semiconductor industry.
Training Highlights:
- DFT Fundamentals and testability concepts for VLSI designs
- Fault models: Stuck-at, Transition Delay, and Path Delay
- SoC Scan Architecture and types of scan designs
- ATPG DRC Debug and Simulation Debug
- JTAG, MBIST (Memory Built-In Self Test), and LogicBIST techniques
- Test Compression techniques using TestKompress
- Hierarchical Scan Design and DFT Diagnosis
Hands-On Training:
- Work on a complex SoC design with multiple embedded memory blocks
- Apply MemoryBIST (MBIST) to test embedded memories in real SoC environments
- Boundary Scan implementation to manage MBIST controllers with minimal external pins
- ATPG pattern generation for multiple fault models: Stuck-at, Transition Delay, and Path Delay
- Simulation-based validation of compressed test patterns using Tessent
Assignments & Practice:
- Extensive assignments covering ATPG, Scan Insertion, Test Compression, and JTAG
- Multiple test cases and real-world scenarios using MentorGraphics Tessent tool
- Practical exercises fully aligned with current semiconductor industry DFT requirements
Training Delivery:
- Concept-focused sessions with real-time hands-on lab practice
- Delivered by experienced trainers from the DFT and semiconductor domain
- Strong emphasis on basic concepts, interaction sessions, important notes, and structured assignments
Program Highlights:
- In-depth, industry-relevant understanding of complete DFT methodologies and testability flows
- Hands-on learning with advanced fault models, scan architecture, and SoC-level DFT implementation
- Strong focus on ATPG, Scan Design, BIST, Test Compression, and Simulation Debug
- Ideal for fresh graduates and engineering students targeting DFT engineer roles in semiconductor companies
- Suitable for VLSI design and verification engineers planning to transition into the DFT domain
Institute Info:
- Offered by VLSIGuru, established in 2012
- Trained over 10,000+ students for semiconductor careers
- Affordable in-class DFT Training in Bangalore
- Online DFT Training available for students and professionals outside Bangalore
- Tool access provided for 12 months after course completion, with provision to extend further
Detailed Overview
DFT (Design for Testability) is a critical discipline in the VLSI semiconductor industry that involves using Scan, ATPG, JTAG, and BIST techniques to add testability to hardware designs. These techniques are used to develop and apply structured tests to manufactured hardware, helping detect real-world manufacturing defects such as stuck-at-0, stuck-at-1 faults, transition delay faults, and path delay faults — ensuring silicon quality and production yield.
VLSIGuru's DFT Training covers all aspects of the testability flow including DFT fundamentals, fault models, SoC Scan Architecture, scan types, ATPG DRC debug, ATPG simulation debug, and DFT diagnosis. The course also covers JTAG, MemoryBIST (MBIST), LogicBIST, Scan and ATPG, test compression techniques, and hierarchical scan design — giving students complete coverage of the DFT domain.
As part of the hands-on training, a complex SoC design example with multiple embedded memory blocks is used as the reference design for learning all testability techniques. MBIST is applied to test embedded memories, while Boundary Scan is used to control MBIST controllers — minimizing the need for extra external test pins. ATPG test patterns are generated for multiple fault models including Stuck-at, Transition Delay, and Path Delay. TestKompress techniques are applied to compress test patterns, reducing test time, minimizing IO pin requirements, and lowering tester memory consumption on the production test floor. All compressed patterns are validated through simulation.
The DFT Training course is structured to meet current semiconductor industry requirements, with multiple hands-on projects based on Scan insertion, ATPG pattern generation, JTAG, and MBIST using the MentorGraphics Tessent tool — the industry's most widely used DFT tool, deployed by more than 80% of semiconductor companies globally. Students gain access to the Tessent tool at the institute for 12 months after course completion, with an option to extend further.
VLSIGuru, established in 2012, has helped 10,000+ students build successful careers in the semiconductor industry. The institute offers affordable DFT Training in Bangalore and Online DFT Training for students and professionals across India and beyond.
VLSI Design flow
- Specification
- RTL coding, lint checks
- RTL integration
- Connectivity checks
- Functional Verification
- Synthesis & STA
- Gate level simulations
- Power aware simulations
- Placement and Routing
- DFT
- Custom layout
- Post silicon validation
Digital Design - Deep dive
- Combinational logic
- Number systems
- Radix conversions
- K-maps, min-terms, max terms
- Logic gates
- Realization of logic gates using mux's and universal gates
- Compliments (1/2/9/10's complement)
- Arithmetic operations using compliments
- Boolean expression minimization, Dmorgan theorems
- POS and SOP
- Conversion and realization
- Adders
- Half adder
- Full adder
- Subtractor
- Half subtractor
- Full subtractor
- Multiplexers
- Realizing bigger Mux's using smaller Mux's
- Implementing Adders and subtractors using Multiplexers
- Decoders and Encoders
- Implementing Decoders and Encoders using Mux and Demux
- Bigger Decoder/Encoder using smaller Decoder/Encoder
- Comparators
- Implementing multi bit Comparators using 1-bit Comparator
- Sequential logic
- Latch, Flipflop
- Latch, Flipflop using Gates or Mux's
- Different types of FFs
- FF Truth table
- Excitation tables
- Realization of FF's using other FF's
- Applications of FF's, Latches
- Counters
- Shift registers
- Synchronizers for clock domain crossing
- FSM's
- Mealy, Moore FSM
- Different encoding styles
- Frequency dividers
- Frequency multiplication
- STA
- Setup time, Hold time, timing closure
- fixing setup time and hold time violations
- Launch flop, capture flop
Linux operating system
- Installing Linux platform in Windows
- Linux basics
- Linux versus Windows
- Linux Terminal
- File and Directory management
- Changing file permissions
- Absolute path and relative path
- Working with directories
- GVIM – major keyboard shortcuts
- Text display commands
- Root configuration files
- Environment variables
- Text processing commands
- grep, fgrep
- xargs
- SEd
- AWK
- Pipes and filters
- Connecting to server
- Process management
- LSF
- Ping
- FTP
- CTAGs
- File compress and extract
- Soft links
TCL Scripting
- Introduce TCL
- Why TCL?
- TCL Script Processing
- Understand TCL uses and strengths
- Writing simple TCL scripts
- TCL for VLSI scripting
- TCL: Main Features
- TCL in EDA
- TCL shell (tclsh)
- Working with TCL scripts (UNIX)
- TCL Interpreter in SoC Design Tools
- TCL Scripting for SoC Design
- TCL Commands
- Variables
- Substitution and Command Evaluation
- Operators
- Mathematical Functions
- Procedures
- Control flow: if, if-else, switch, for, foreach, while, break and continue string, string operations
- List, List manipulation
- Arrays, array methods
- Working with files
- Command line arguments
- Regular expressions
- Complete TCL Scripts
- TCL Packages
Verilog basics
- Verilog language constructs
- Combinational logic implementation using Verilog
- Testbench coding for combinational logic
- Sequential logic implementation using Verilog
- Testbench coding for sequential logic
- Clock generation with frequency, Jitter and duty cycle
- Memory coding and test bench setup
- Running simulations, analysing waveforms, debugging concepts
Key Features
Who All Can Attend This DFT Training?
This training is ideal for professionals aiming to specialize in testability design techniques for VLSI and SoC development. It is suitable for both working engineers and fresh graduates looking to build careers in semiconductor testing and design.Pre-requisites To Take Design for Testability (DFT)
- There are no prerequisites for DFT training, however, having a basic understanding of Digital logic and VLSI design flow is an added advantage.
High Demand for Design for Testability (DFT)
Know about the Growing VLSI industry
DFT Engineers are highly valued in semiconductor companies for optimizing test coverage and reducing silicon defects. Salaries grow significantly with expertise in scan insertion, ATPG, MBIST, and experience using tools like Synopsys DFT Compiler and Tessent. Bangalore, Hyderabad, and Noida offer the highest compensation.
₹8 LPA
₹12 LPA
₹16 LPA
₹20 LPA
₹25 LPA
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Hands-On Learning with Real-Time Projects
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Explore a wide range of VLSI and Embedded Systems courses to get industry-ready.
50+ industry oriented courses offered.
Explore a wide range of VLSI and Embedded Systems courses to get industry-ready.
50+ industry oriented courses offered.
