Course Overview

DFT (Design for Testability) Training – Summary

Duration: 8 months comprehensive program

Tools: 

• Synopsys TetraMax
• MentorGraphics Tessent

Placement Support: Institute provides placement support till candidate gets a JOB

Training Highlights:

• DFT Fundamentals
• Fault models: Stuck-at, Transition Delay, and Path Delay
• SoC Scan Architecture and Types of Scan Designs
• ATPG DRC Debug and Simulation Debug
• JTAG, MBIST (Memory Built-In Self Test), and LogicBIST techniques
• Test Compression Techniques using TestKompress
• Hierarchical Scan Design and DFT Diagnosis

Hands-on Training:

• Work on a complex SoC design with multiple memory blocks
• Apply MemoryBIST to test embedded memories
• Boundary Scan used to manage MBIST controllers with fewer external pins
• ATPG Pattern Generation for multiple fault models
• Simulation-based validation of compressed test patterns

Assignments & Practice:

• Extensive assignments for ATPG, Scan insertion, compression and JTAG
• Multiple test cases and scenarios using Tessent tool
• Practical exercises aligned with current industry needs

Training Delivery:

• Concept-focused sessions with real-time lab practice
• Delivered by experienced trainers from the DFT domain

Program Highlights:

• In-depth, industry-relevant understanding of DFT methodologies
• Hands-on learning with advanced fault models and scan architecture
• Focus on ATPG, Scan, BIST, Compression, and Simulation Debug
• Institute Info:
• Offered by VLSIGuru, established in 2012
• Trained over 10,000+ students
• Affordable in-class training in Bangalore
• Online training available for students outside Bangalore

Detailed overview:

DFT(Design for Testability) involves using SCAN, ATPG, JTAG and BIST techniques to add testability to the Hardware design. These techniques are targeted for developing and applying tests to the manufactured hardware. There tests in turn help catch manufacturing defects like stuck at 0, 1 faults, and transition delay faults etc.

DFT Training will focus on all aspects of testability flow including DFT basics, various fault types, SOC Scan Architecture, different scan types, ATPG DRC Debug, ATPG Simulation debug, and DFT diagnosis. DFT Training course will also focus on JTAG, MemoryBIST, LogicBIST, Scan and ATPG, test compression techniques and Hierarchical scan design.

As part of DFT Training, a complex design example with variety of memories spread around the design used as a reference for learning all testability. While MBIST used to test memories. Boundary scan is a requirement for designs, used to control the MBIST controllers that are created to minimize the need for having extra external pins to run the memory tests. ATPG test patterns will be created for various different fault models like stuck-at, transition delay, path delay fault models. Various TestKompress techniques will be used to compress test patterns to ensure patterns can be applied on minimal number of IO pins used during test. Compressed test patterns will run more quickly on the production test floor and require less tester memory. Patterns are validated through Simulations.

DFT Training course is designed as per the current industry requirements with multiple hands on projects based on Scan, ATPG, JTAG and MBIST. DFT Training will help student with in-depth knowledge of all testability techniques. Hands-on project will involve creating large number of test cases for various aspects like Scan insertion, Compression, JTAG and ATPG pattern generation using Tessent tool. More importance is given to basic concepts, interaction sessions, hands-on, important notes and assignments.

MentorGraphics Tessent tool is used for training. As per industry survey, it is used by more than 80% companies for DFT. Student will have access to tool at the institute for 12 months after course completion, with a provision to extend beyond.