The PCIe Physical Layer UVC Development course focuses on designing and developing UVC components for PCIe AXI, DLL–PL, and PL–PHY interfaces. Participants will learn how to build reusable verification components and integrate them with Physical Layer RTL to create a complete, working verification testbench.

The course also covers the fundamentals of Transaction Layer RTL coding, along with testbench architecture design, test plan creation, and testcase development. Emphasis is placed on understanding how different PCIe layers interact and how verification environments are structured in real-world projects.

Training sessions include hands-on development of sequences for AXI, TL–DLL, and PL–PHY interfaces, and demonstrate how these sequences are used to build meaningful and scalable testcases. Learners will gain practical exposure to debugging testcases, identifying failures, and analyzing waveform and log-based issues.

This course is designed to strengthen core PCIe PHY verification concepts and provide practical implementation experience. While the training code demonstrates real verification workflows and concepts, learners should note that the UVC code structure may not be an exact one-to-one match with proprietary industry-standard UVC implementations, but the methodology and concepts align closely with industry practices.