Advanced Physical Design Training

Advanced Physical Design Training is a 4.5-month program for working professionals to master the full Physical Design flow (Netlist to GDSII) at the 14nm node. It includes hands-on training with Synopsys and Cadence tools, 24×7 tool access, and 100% placement support.

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Course Overview

Advanced Physical Design Training Overview

Course Overview

Advanced Physical Design Training – Summary

Duration: 5 months advanced program

Tools: Synopsys Custom Compiler and Cadance Virtuoso (DC, ICC II, StarRC, PT, ICV)

Placement Support: Institute provides placement support till candidate gets a JOB

Training Highlights:

Advanced Physical Design flow from Netlist to GDSII at 14nm

Designed specifically for working professionals

Assumes prior knowledge of CMOS, Digital Design, and Fabrication

Hands-on training using industry-preferred Synopsys Custom Compiler and Cadance Virtuoso tools

Focus on critical industry issues and practical debugging methods

Technical Coverage:

Complete Physical Design Flow: Synthesis to GDSII

IR Drop Analysis and Power Integrity Techniques

Physical Verification using ICV

Timing Analysis using PrimeTime

Place & Route using ICC II and extraction using StarRC

Hands-on Training:

Multiple real-time projects using Synopsys Custom Compiler and Cadance Virtuoso Tools

Debug and optimization of real-world PD issues

Industry scenarios for floorplanning, placement, CTS, routing, and closure

Training Delivery:

Focused theory with in-depth lab sessions

Training delivered by experienced industry professionals

Program Highlights:

Designed to upskill professionals for 14nm and below process nodes

Emphasis on practical issues, power integrity, and closure techniques

Real-time debug-oriented training with job-ready assignments

Institute Info:

Offered by VLSIGuru, established in 2012

Trained over 10,000+ students

Affordable in-class training in Bangalore

Online training available for students outside Bangalore

 

Detailed overview:

Advanced Physical Design Training is a 5 months course meant for working professionals to gain in-depth knowledge of all aspects of Physical design flow from Netlist to GDSII including all the aspects of Physical design flow at 14nm. Course assumes that student is familiar with fundamental concepts of Physical design like CMOS, Digital design and fabrication. Course involves multiple hands on projects using Synopsys Custom Compiler and Cadance Virtuoso tools(DC, ICC II, Star RC, PT, ICV). Synopsys Custom Compiler and Cadance Virtuoso flow is among widely used PnR flow in industry.


Physical Design training emphasizes on issues faced in industry level projects and how to resolve those issues. Training also focus on other aspects of VLSI back end flow including Synthesis, IR drop analysis and Physical verification. Training will provide participants with expertise on entire back end flow, making sure that candidate fits in to various job requirements.

Syllabus
Physical Design (Advanced) Modules

SYNOPSYS,CADENCE {synopsys ICC II, RedHawk, Primetime, StarRC, Design Compiler, ICV}

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Key Features

Gain in-depth expertise in 14nm Physical Design flow tailored for working professionals
Work on hands-on projects using Synopsys tools to learn through real-world implementation
Learn an industry-focused curriculum designed to solve practical VLSI design challenges
Understand the complete VLSI back-end flow from synthesis to verification
Get trained by expert instructors with real industry experience
Advance your career by gaining skills relevant to multiple job roles in the VLSI domain

Who All Can Attend This Advanced Physical Design Training?

This training is ideal for VLSI professionals and graduates aiming to specialize in back-end design at advanced technology nodes. It’s best suited for those involved in layout, timing, and physical implementation of SoCs.
Physical Design Engineers
STA Engineers
ASIC Design Engineers
VLSI Engineers
SoC Implementation Engineers
RTL to GDSII Engineers
Backend Design Engineers
CAD Engineers
Design Verification Engineers
Graduate Engineers aspiring to enter VLSI backend design
Physical Design Engineers
STA Engineers
ASIC Design Engineers
VLSI Engineers
SoC Implementation Engineers
RTL to GDSII Engineers
Backend Design Engineers
CAD Engineers
Design Verification Engineers
Graduate Engineers aspiring to enter VLSI backend design

Pre-requisites To Take Physical Design (Advanced)

  • Good understanding VLSI Technology basics(CMOS, FinFET, etc)
  • Digital design concepts

High Demand for Physical Design (Advanced)

Know about the Growing VLSI industry

Physical Design Engineers are critical for RTL to GDSII implementation. Engineers skilled in floorplanning, placement, clock tree synthesis (CTS), routing, and signoff analysis at advanced nodes (14nm, 7nm) see faster career growth. Familiarity with tools like ICC2, Innovus, and PrimeTime boosts salary potential.

Annual Salary

₹7 LPA

₹12 LPA

₹16 LPA

₹20 LPA

₹28 LPA

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VLSIGuru
VLSIGuru is a top VLSI training Institute based in Bangalore. Set up in 2012 with the motto of ‘quality education at an affordable fee’ and providing 100% job-oriented courses.
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