Course Overview

Custom Layout Training with multiple projects at 18nm tech node – Summary

Duration: 8 months comprehensive program

Tools:Synopsys Custom designer and Cadence Virtuoso tools (24×7 Tool access)

Placement Support: Institute provides placement support till candidate gets a Job

Training Highlights:

Analog Layout, Memory Layout, Standard Cell and IO Layout Design

CMOS, FinFET technologies and various memory architectures

Detailed understanding of VLSI Design Flow and Advanced Digital Design

Linux commands, scripting, version control, and soft skills for interviews

Core Electronics Foundation:

Semiconductors, Ohm’s Law, Kirchhoff’s Laws

Diode and MOSFET operation with second-order effects

FinFET technology and complete IC fabrication process

Layout Techniques:

Standard Cell Layout Design

Memory Layout and IO Layout for multiple architectures

Analog Layout Techniques including Matching and Noise Mitigation

Analysis of Electro Migration, IR Drop, Antenna Effect, WPE, LOD, Latch-up, and ESD issues

Hands-on Training:

20+ lab sessions and detailed assignments across all layout areas

Real-time projects in Standard Cell, IO, Memory, and Analog Layout

Analog Layout Projects:

Common Centroid and Interdigitation Techniques

Resistor and Capacitor Matching

Opamp Layout, Current Mirrors, PLLs, ADCs, DACs

Bandgap References, Temperature Sensors

Current and Voltage Bias Lines, Large Drivers, LNAs, Mixers

Sense Amplifier and Bit Cell Development

Training Delivery:

Comprehensive theory + lab sessions guided by industry experts

Practical exposure using real-time design examples

Program Highlights:

End-to-end Custom Layout expertise from basics to advanced analog design

Emphasis on failure mechanisms and robust layout strategies

Industry-standard practices and tools throughout the course

Institute Info:

Offered by VLSIGuru, established in 2012

Trained over 10,000+ students

Affordable in-class training in Bangalore

Online training available for students outside Bangalore

Detailed overview:

Custom Layout Training is a 8-month course done using both Synopsys custom compiler and Cadence Virtuoso tools. it provides deep technical expertise in all major layout domains including Analog, Memory, Standard Cell, and IO layout.

The course prepares students in both theoretical and hands-on aspects of VLSI physical design, including advanced CMOS and FinFET layouts, failure mechanisms, fabrication processes, and analog layout techniques. Extensive hands-on labs and projects build the necessary skills to succeed in layout design roles in the VLSI industry.

Custom layout training is a 8 months course focused on all the aspects of layout including Analog layout, Memory layout, Standard cell layout and IO layout.

Custom layout design course ensures that the student is prepared on all the essential aspects of Custom layout including VLSI Design flow, advanced digital design, CMOS, FinFET, various memory architectures, Standard cell, IO’s and detailed analog layout techniques. Course also includes training on Linux commands, version control, scripting and soft skill for effective interview performance.

Course also includes detailed sessions on semiconductors, Ohms law, Kirchoff law’s, Diode-operation, MOSFET’s, MOSEFT operations, second order effects, FinFET’s, and detailed fabrication process, which is followed by assignments and hands on projects.

Course also covers layout basics, hands on standard cell layouts, IO layout and memory layout for different architectures. Followed by various analog layout techniques with detailed discussion on Mismatches & Matching, Noises & Coupling, various failure mechanisms which includes Electro migration, IR drop, LOD & Stress effects, WPE, Antenna Effects, Latch up, ESD. Course includes 20+ detailed labs & assignments covering all aspects of custom layout with multiple hands on projects.

Analog layout techniques involve multiple hands on projects covering various concepts such as common centroid, inter digitation, resistor matching, capacitor matching and opamp circuits, current mirrors, PLL’s, ADC’s, DAC’s, Bandgap, Temperature sensors & Biases -> Current & Voltage bias lines, Large drivers, LNA & Mixers, and Sense amplifier & Bit cell development.