Advanced DFT(Design for Testability) course is a 4 months course providing in-depth exposure to entire DFT flow including SCAN, compression, ATPG, simulations, JTAG and BIST techniques to add testability to the Hardware design. Participants will get hands on exposure to Tessent tool for all the aspects of DFT flow.

DFT Training focused on all aspects of testability flow including DFT basics, various fault types, SOC Scan Architecture, different scan types, ATPG DRC Debug, ATPG Simulation debug, and DFT diagnosis. DFT Training course will also focus on JTAG, MemoryBIST, LogicBIST, Scan and ATPG, test compression techniques and Hierarchical scan design.

Highlights:

• Design with 17K+ flip flops
• Exposure to all the aspects of flow both at RTL level and gate level netlist
• Multiple lab exercises on each aspects of the flow
• Exposure to issues faced in industry level project and how to resolve those issues