Syllabus
Course Overview
Projects
Schedule
Demo
FAQs
Trainer
Certificate
Syllabus
- Layout Editor Tool
- Understanding the schematic symbols and parameters
- Creating and managing libraries and cell
- Commands for Layout editing.
- Commands for schematic editing.
- Verification : DRC and LVS
- Antenna effect, latchup, Electromigration, IR Drop
- Analog Layout of OpAmp, Current Mirror, PLL, ADC, and DAC
- Resistor, Capacitor layout techniques
- CMOS and BiCMOS layout techniques
- Standard Cell Layout : Inverter, AND, OR, NAND, NOR, AOI, OAI, Latches, and Flop
- Mismatches & Matching.
- Failure Mechanism : Electro migration, IR drop, LOD & Stress effects, WPE, Antenna Effects, Latch up, ESD (with High voltage rules, EOS effects).
- Noises & Coupling.
- Different Types of process – Advantages & Disadvantages – Planar CMOS, FD-SOI, SOI, Bi-CMOS, Gallium Arsenide, Silicon-Germanium, Finfet.
- Full Chip Construction, Scribe Seal, Pad Frame, Integration and guidelines.
- Packaging.
- Std Cell & Memories.
- IO Layout Guidelines : High speed IOs and High Speed Interfaces.
- Sense amplifier & Bit cell development
- Why memory layout different than analog layout
- Memory layout flow
- Types of memory layout (SRAM/DRAM/ROM)
- Introduction to SRAM memory layout
- Fixing few manually created leaf-cell errors which impact
- Abutment issues
- Impact of IR, EM and DFM .
- SRAM memory design architecture
- Words line and address line
- SRAM rows and column design
- Building blocks of SRAM
- Memory Bit cell
- Row decoder
- Word line driver
- Sense amplifier
- Control block
- Misc digital logic.
- Pitch Calculation for blocks.
- Power Planning
- High speed Analog Layout
- RF Layout guidelines with Transmission lines and inductor concepts
- Handling clocks
- Analog Circuits & Layout guidelines
- Single & Multi stage differential opamp layout
- current mirror layout
- PLL, DLL and Oscillators
- LDO and other regulators
- ADCs & DACs
- Bandgap, Temperature sensors & Biases -> Current & Voltage bias lines
- Large drivers
- input pair, differential routing, Power routing, offset minimising
- Power/Signal IR Drop
- cross-talk and coupling
- Electrostatic Discharge
- Deep Sub-micron Layout Issues
- Shallow Trench Isolation (LOD)
- Well Proximity Effect
- Design Rule Checks
- Layout Versus Schematic (LVS)
- Electrical Rule Checks (ERC)
- Antenna Checks
- Latch-up
- Reliability checks like EM and IR analysis
- Design for manufacturability (DFM)checks
- Electrostatic discharge (ESD) path checks
- Assignments and multiple hands on projects
- Best Practices & Interview Questions.
Course Overview
Course Overview
Advanced Custom and analog layout training is a 4 months course targeted for working professional planning to pursue career as a layout design engineer or wants to learn advanced aspects of Custom and analog layout. Training focused on all the aspects of layout including Analog layout, Memory layout, Standard cell layout and IO layout.
Course also includes detailed sessions on layout basics, hands on standard cell layouts, IO layout and memory layout for different architectures. Followed by various analog layout techniques with detailed discussion on Mismatches & Matching, Noises & Coupling, various failure mechanisms which includes Electro migration, IR drop, LOD & Stress effects, WPE, Antenna Effects, Latch up, ESD. Course includes 20+ detailed labs & assignments covering all aspects of custom layout with multiple hands on projects.
Analog layout techniques will involve multiple hands on projects covering various concepts such as common centroid, inter digitation, resistor matching, capacitor matching and opamp circuits, current mirrors, PLL’s, ADC’s, DAC’s, Bandgap, Temperature sensors & Biases -> Current & Voltage bias lines, Large drivers, LNA & Mixers, and Sense amplifier & Bit cell development.
Projects
Below is the list of projects student will be doing as part of four months training. Student will be doing all these projects from scratch. These projects will provide student with expertise on par with a 2 to 3 years experienced engineer, in terms of all the skill set required.
By working on below projects, student will get familiar with:
- Complete layout flow including
- Floor planning
- Schematic
- Layout
- Physical verification
Description : Schematic, Layout design and verification for standard cell for NOT, NAND, NOR, AND, OR gate and Buffer.
Role : Layout Design and Layout Verification.
Challenges : Involved in placement, routing by taking care of minimum area and Verification.
Tools Used : Synopsys Custom Designer & IC Validator (for DRC/LVS).
Technology Node: 28nm
Description : Designed the Layout for Level Shifter.
Role : Layout Design and Layout Verification.
Challenges : Involved in placement, routing by taking care of minimum area and Verification.
Tools Used : Synopsys Custom Designer & IC Validator (for DRC/LVS).
Technology Node: 28nm
Description : Designed the Layout for Schmitt Trigger.
Role : Layout Design and Layout Verification.
Challenges : Involved in placement, routing by taking care of minimum area and Verification.
Tools Used : Synopsys Custom Designer & IC Validator (for DRC/LVS).
Technology Node: 28nm
Description : Single stage Op-Amp designed, one with NMOS differential pair and the other with PMOS differential pair whose input and output are Shielded. Common Centroid matching technique was used while implementing differential input pair. Taken care of Electro migration to manage current in the last stage which is a high gain stage and proper care was taken to avoid latch up.
Role : Layout Design for OpAmp and Layout verification.
Challenges : Involved in placement, matching of MOS devices, routing by taking care of Electro migration and Layout verification.
Tools Used : Synopsys Custom Designer & IC Validator (for DRC/LVS).
Technology Node: 28nm
Description : Designed layout for the 4-bit Flash Analog to Digital converter. Main Challenge was matching of the resistors as any variation in the Resistance would results in the improper output.
Role : Layout Design for Block and Top level.
Challenges : Floor-planning considering different devices and precise resistors Matching and their Internal routing constraints. Routing by taking Care of resistance, IR and Top-level layout verification.
Tools Used : Synopsys Custom Designer & IC Validator (for DRC/LVS).
Technology Node: 28nm
Description : Designed the layout for 4 bit Digital to Analog converter. Main Challenge was the matching of the resistors.
Role : Layout Design for block level. Adjusted M1 and M2 pattern errors by adding fill cells and metal fills cleaned DRC, LVS by using the CPDS.
Challenges : Floor-planning considering resistor. Routing is one by taking care of IR, symmetry and top-level layout verification.
Tools Used : Synopsys Custom Designer & IC Validator (for DRC/LVS).
Technology Node : 28nm
Description : Designed the BGR with startup circuit. Main challenge was the matching of the resistors and symmetric routing.
Role : Layout Design for block level (BGR).
Challenges : Floor-planning considering different devices and BJTs and their internal routing constraints. Routing by taking care of Electro-migration, Latch-up and IR and top-level layout verification LVS/DRC.
Tools Used : Synopsys Custom Designer & IC Validator (for DRC/LVS).
Technology Node: 28nm
Description : Designed the Layout for LDO using single stage Op-Amp as error amplifier with large PMOS and feedback resistors. In which matching, area, Electro migration and shielding constraints are taken into consideration. Proper care was taken about Electro migration to manage high current in the last stage which is a high current stage.
Role : Layout Design for block level and top level.
Challenges : Floor-planning considering different blocks and their internal routing constraints. Routing by taking care of electro migration, shielding symmetry, IR and top-level layout verification LVS/DRC.
Tools Used : Synopsys Custom Designer & IC Validator (for DRC/LVS).
Technology Node : 28nm
Technology Node : 28nm
Role : layout of VCO, Charge pump, phase detector Cleaned DRC, LVS of the above blocks
Challenges : Sharing of devices, area minimization and routing issues. Also, matching must be there in layout by proper techniques.
Technology Node : 28nm
Role : Adjusted M1 and M2 pattern errors by adding fill cells and metal fills cleaned DRC, LVS.
Challenges : M1 layer is inbuilt present in Active devices, so M1 errors has to be cleaned without disturbing a floor plan. Also, need to clean the errors regarding higher metals
Schedule
Course is offered in both classroom and online training
| Custom and Analog Layout Training | |
|---|---|
| Duration | 4 months |
| Next Batch | 04/November |
| Schedule | |
| Saturday & Sunday(9AM – 5PM) India time | |
| 9AM – 1PM (Theory session offered by trainer) | |
| 2PM – 5PM (Lab & tool based session guided by trainer). Students from US will get support in different time. | |
| Students can also get support on complete project flow during weekdays in evenings. | |
| New batch starts | Every 8 Weeks |
| Tools | Synopsys Custom Designer, IC Validator |
| Mode of training | Class room training and Live online training sessions |
| Tool Access | Tool access for complete course duration |
| Batch Size | 15 |
| Assignments | 10 |
Demo
Theory Demo
Lab Demo
FAQs
- Course presentations for all topics
- Session notes
- Lab documents with detailed steps
- User guides
- Expertise on Digital & Analog design concepts
- Exposure to basic layout concepts
Trainer
Experienced Trainer
- 6+ years of rich experience of working in all aspects of custom layout from Analog, Memory, IO and Standard cell at various technology nodes
- Senior Director in a reputed Design company
Certificate
Play Video
- 1-1 Dedicated Mentor Support
- 24/7 Tool Access
- Multiple mock interviews
- Industry Standard Projects
- Support with resume update