• Processor significance in SOC
• Why RISCV
• RISCV ISA
• RISCV basics
• RISC-V architecture
• Sub components
• Instruction Fetch unit, Decode unit, execution unit
• pipelining stages
• Instruction set architecture (ISA)
• Instruction summary
  
  • RV32I Base Integer Instruction set
  • RV32E Base Integer Instruction Set
  • RV64I Base Integer Instruction set
  • RV32/64G Instruction set listings
  • RISC-V Assembly programming summary
  • M Standard Extension for Integer
  • Multiplication and Division
  • A Standard Extension for Atomic Instructions
  • F Standard Extension for Single-Precision Floating-point
  • D Standard Extension for Double-Precision Floating-point
• Multiple hands on example on RISC-V based code implementation
• RV32I base instruction
• Exceptions, Traps and Interrupts
• Sample examples using RISC-V assembly language
  
  • prime number generation
  • Multiple examples on RISC-V assembly instruction coding
• RISC-V Privilege levels
• Switching between privilege levels
• Control and status registers
• Machine mode
  
  • Physical memory protection
  • Physical memory attributes
• Supervisor mode
• User mode
• MMU
  
  • VA to PA translation
  • Page faults
  • Translating Virtual Addresses

Course Overview

Experienced Trainer

• Multiple trainers, with experience of working on multiple SOC tape outs. All working in top-3 product companies.