Course Overview
Syllabus
Schedule
FAQs
Course Material
Trainer
Course Overview
Online course in UVM & OVM for Functional Verification (VT-VMO) is structured to enable engineers develop their skills in full breadth of UVM & OVM features in complex testbench development. VT-VMO course is targeted for verification engineers who are proficient with SV based functional verification and are looking to explore UVM & OVM based verification. Course has been framed in a way to make UVM & OVM learning a fun and interesting activity. Every aspect of course is supported with multiple examples to enable easier & quicker understanding. Course also covers multiple industry standard projects, all of these executed from scratch. Lab sessions are planned at regular intervals to enable student work on these projects from scratch with trainer guidance. Below is quick overview of what is covered as part of VT-VMO.
- UVM & OVM Base class and Macro usage with detailed examples on each construct usage
- AHB Protocol, AHB UVC development & AHB I/C functional verification
- Register layer development for USB2.0
- USB2.0 Core Functional verification
Syllabus
- AHB Interconnect verifiation project used as reference design to learn UVM & OVM
- AHB Interconnect will be verified from scratch while teaching all aspects of UVM
- UVM/OVM TB Architecture
- UVM Class Library, Macros, Utilities
- UVM Factory, Synchronization, Containers, Policies
- UVM Components, Comparators, Sequences, Sequencers
- Stimulus Modeling, Sequences & Sequencers
- Creating UVCs and Environment
- Simulation Phases
- TLM Overview, Components
- Configuring TB Environment
- Register Layer, Configuration DB & Resource DB
- Connecting multiple UVCs
- Creating TB infrastructure
AHB2.0 is an AMBA protocol used for medium performance applications. I was part of UVC development team. UVC was developed to work as both master and slave. Developed all the UVC components and validated UVC for various AHB features.
What student learns in this project:
What student learns in this project:
- Develop UVC Architecture to be compatible with both master and slave behavior
- List down AHB features and develop testplan for validating AHB UVC
- Develop AHB UVC components
- Integrated AHB Master UVC with slave UVC
- Develop sanity testcases and debug the same
- Develop functional tests and debug the same
AHB Interconnect is a configurable design used for connecting multiple AHB based masters to various AHB slaves. Design can be configured can multiple masters and multiple slaves.
What student learns in this project:
What student learns in this project:
- Develop TB Architecture to be compatible with configurable number of master and slaves
- List down design features and develop testplan
- Integrate APB UVC and AHB UVC to set up whole TB
- Configuring AHB UVC to work as a master or slave
- Develop sanity testcases and debug the same
- Develop functional tests and debug the same
- Regression setup and coverage report generation
- Listing down registers
- Creating Register Model
- Integrating Register Model in to Testbench
- Using Register Model to create tests
- Using Register Model in scoreboard
- UVC Development for AXI Protocol
- PCIe LTSSM FSM Verification
- Register Model Development for SPI Core
Schedule
| Course | UVM course in Functional Verification |
|---|---|
| Duration | 8 weeks |
| Next Batch | 25/Oct |
| Demo Session | 25/Oct (9AM – 1PM) |
| Registration | 26/Oct |
| Schedule | Both Saturday & Sunday (9AM – 5PM IST) |
| 9AM to 1PM (Trainer led sessions covering theory and labs) | |
| 1:45PM to 5PM (Mentor guided sessions covering labs assignments and doubt clarifications). Online students from US will get support in different time. | |
| Course repeats | Every 16 Weeks |
| Fee | INR 14000 + GST@18% |
| Tool | Questasim & VCS |
| Online training using live training sessions | |
| Certificate | Issued based on 50% assignment completion as criteria |
| Batch Size | 20 |
| Assignments | 20 |
| Admission criteria | Student need to undergo evaluation test based on Verilog & SV |
| Placement support | Interview opportunity in at least 6 companies |
| Trainer | 12+ Years exp in RTL design & Functional verification |
FAQs
- Course presentations for all topics
- Session notes
- Lab documents with detailed steps
- User guides
- Yes, Course fee also includes support for doubt clarification sessions even after course completion
- You have option to mail you queries
- Option to meet in person to clarify doubts
- Most of the times, reasoning for any institute to charge higher fee(excess of 1 lakh) is tool cost is high. It is not true.
- VLSIGuru believes in creating an educational model that is affordable and sustainable in the long run. We have been running successfully since we started training in 2012 with 3500+ students trained so far. We take pride in the fact that, it is VLSIGuru which made other institutes also to offer courses in 30K to 50K range, otherwise it used to be much higher.
- Institute owns the office facility, hence we avoid rental expense. Keeping it aside, we also find it difficult to comprehend why course fee should be in excess of 1 Lakh.
- Good understanding VLSI Technology basics(CMOS, FinFET, etc)
- Digital design concepts
- Each session of course is recorded, missed session videos will be shared
- Yes, You will have option to view the recorded videos of course for the sessions missed
- You will have option to repeat the course any time in next 1 year
Course Material
Course Material Shared:
- UVM User Guide
- UVM Checklist
- UVM Lab Examples
- AHB UVC Code
- AHB Interconnect Testbench Code
- SPI Register Layer code
- USB2.0 Core testbench Code
Trainer
Trainer Profile
- 10+ years of rich experience of working in Functional Verification domain across various mobile, networking, high speed peripheral domains.
- Experience of working on functional verification of Multiple Complex SOCs, multiple Sub systems
- Experience of working on multiple complex module level projects
- 1-1 Dedicated Mentor Support
- 24/7 Tool Access
- Multiple MOCK Interviews
- Industry Standard Projects
- Resume Preparation