Syllabus
Course Overview
Projects
Schedule
Demo
FAQs
Trainer
Certificate
Syllabus
- Duration: 10 months
- Phase#1 – 2.5 months
- Advanced Digital design
- GVIM text editor
- Verilog
- Linux basic commands
- Phase#2 – 3.5 months
- System Verilog
- UVM
- Linux advanced commands – hands on
- Soft skill training
- AXI protocol and TB development
- Python
- ASIC flow and SOC verification concepts
- Candidate gets placement support from this stage.
- Phase#3 – 4 months
- MTech Project or Internship project
- Combinational logic
- Number systems
- Radix conversions
- K-maps, min-terms, max terms
- Logic gates
- Realization of logic gates using mux’s and universal gates
- Compliments (1/2/9/10’s complement)
- Arithmetic operations using compliments
- Boolean expression minimization, Dmorgan theorems
- POS and SOP
- Conversion and realization
- Adders
- Half adder
- Full adder
- Subtractor
- Half subtractor
- Full subtractor
- Multiplexers
- Realizing bigger Mux’s using smaller Mux’s
- Implementing Adders and subtractors using Multiplexers
- Decoders and Encoders
- Implementing Decoders and Encoders using Mux and Demux
- Bigger Decoder/Encoder using smaller Decoder/Encoder
- Comparators
- Implementing multi bit Comparators using 1-bit Comparator
- Sequential logic
- Latch, Flipflop
- Latch, Flipflop using Gates or Mux’s
- Different types of FFs
- FF Truth table
- Excitation tables
- Realization of FF’s using other FF’s
- Applications of FF’s, Latches
- Counters
- Shift registers
- Synchronizers for clock domain crossing
- FSM’s
- Mealy, Moore FSM
- Different encoding styles
- Frequency dividers
- Frequency multiplication
- STA
- Setup time, Hold time, timing closure
- fixing setup time and hold time violations
- Launch flop, capture flop
- Verilog language basics
- Verilog : How the language evolved?
- Verilog execution using Modelsim
- Verilog constructs
- Literals
- Data types
- Operators
- Continuous assignments
- Procedural timing controls
- task and functions
- system task and function
- modeling memories and FSM
- Parameters
- Port connections
- Procedural blocks
- Sensitivity list
- State machines
- timescale
- Verilog timing regions
- process
- Blocking and nonblocking statements
- Inferring combinational and Sequential logic
- fork join
- Race conditions
- Synthesis examples
- Inter and Intra delay statements
- Pipelining
- PLI
- compiler directives
- DFF coding using gate level, behavioral
- Counters
- Up counter
- Ring counter
- Johnson counter
- Memory design and verification
- Memory Verilog coding
- Front door access
- Back door access test case coding
- Test case coding and understanding waveforms
- FIFO – Synchronous FIFO and Asynchronous FIFO
- Synchronous FIFO
- Asynchronous FIFO
- Finite state machines
- Mealy and Moore style
- Implicit and Explicit styles of coding.
- Pattern detector – Overlapping, Non-Overlapping, Dynamic
- Overlapping
- Non-Overlapping
- Dynamic
- Traffic light controller
- APB protocol
- Interrupt controller
- SPI controller
- CRC generation
- Functional Verification overview
- Test bench architecture
- Test bench components
- Test bench development : Modularity, Reusability
- Understanding Functional Verification flow
- System Verilog Course overview
- System Verilog language features
- Verilog for TB development
- Verilog Language constructs and shortcomings
- operators, data types
- Literals
- Operators – How things change from Verilog
- Data types – Integer based, string
- Arrays
- Arrays
- Array classification
- Packed and Unpacked Arrays
- Static and Dynamic Arrays
- Multi dimensional Arrays
- Dynamic Arrays
- Associative Arrays
- Queue
- Array of Queues in scoreboard implementation, other complex declarations
- Object Oriented Programming
- Basics of OOP – Class, Object, handle
- Class elements – Properties, methods, constraints
- Properties – 5 attributes in property declaration – rand/randc, signed, static, 2/4 state, data hiding
- Language provided and User defined methods
- Developing Ethernet frame and APB Tx class
- new constructor
- randomize, pre_randomize, post_randomize
- User defined methods – print, copy, compare, pack, unpack
- Encapsulation – Data hiding, local, protected, public
- Inheritance
- Ethernet frame generation example to learn OOP
- Polymorphism – real life usecases
- this, super
- Class forward declaration
- Multiple levels of inheritance
- Abstract class
- Parameterized classes
- Difference from Verilog parameterization
- Parameterization with inheritance – 4 combinations
- Parameterized classes for testbench development
- Static properties and methods
- Interface class
- Constant class property
- Scope resolution operator
- Nested class
- Variable scope
- Object copying – copy by handle, shallow copy, deep copy
- $cast – static and dynamic casting
- Advanced Data types
- Data types – Chandle, event, typedef, struct, union, enum
- Using struct data type for medals tally sorting example
- Typedef for defining complex data types
- Using complex data types in scoreboard development
- Fork join, Inter process synchronization
- Labeling
- Fork join – join_any, join, join_none
- Nested fork
- Labeling fork
- Process, process states
- Inter process synchronization
- IPS constructs – mailbox, event, Semaphore
- mailbox – types, methods
- events – persistant, synchronization examples
- Semaphore – synchronization examples
- Project to learn all SV language constructs
- Project – Memory TB development covering 90% of SV language constructs
- Configurable memory TB development
- Interface – Ports, internal signals, clocking block, modport
- using clocking block to fix design – TB synchronization issues
- Physical interface, virtual interface
- Using interface for design and TB connection
- Program
- Program significance
- How Program differs from Module
- Why Program is redundant?
- Scheduling semantics
- Scheduling semantics
- Task, Function
- Task, function – how they are different from Verilog
- Static & automatic task/functions
- System task and functions
- Constraints, Randomization
- Constraints format
- Constraints type – Simple, distribution, implication, if-else, iterative, variable ordering, soft, unique
- Inline constraints
- Constraints for queue randomization
- Constraints virtual nature
- Randomization
- randcase
- Randomization in class, module
- rand, randc
- Constrained random verification
- Directed verification
- Multiple hands on examples on Constraints and Randomization
- Chip select example using multiple inter related constraints
- new significance for randc
- Functional and code coverage
- Functional Coverage
- What is functional coverage?
- Need for functional coverage
- Where FC comes in functional verification flow?
- How to implement FC?
- Different types of FC?
- Integrating Functional coverage in Test bench
- functional coverage hierarchy
- Different types of coverpoints – simple, cross, transition
- Different types of bins – normal, illegal, ignore
- coverage calculation
- coverage options – auto_bin_max, weigth, at_least, goal, comment, name, per_instance, detect_overlap
- Listing down cover points for a design
- Instance coverage
- Cross coverage with intersect
- FC system task & Functions
- Coverage Driven Verification
- Coverage report analysis
- Cover groups with arguments
- Coverage filter using iff
- Functional coverage types in TB – transaction class coverage, register field coverage, scenario coverage
- Code coverage
- Generating code coverage
- Different types of code coverage – FSM, Conditional, Branch, Expression, Statement, Toggle
- Detailed understanding of code coverage types with examples
- Merging UCDBs, generating coverage reports
- Analyzing coverage report
- Coverage exclusion
- Assertions and Assertion based verification
- Need for assertions?
- Assertion based verification
- Types of assertions
- Immediate assertions
- Concurrent assertions
- Assertion format – antecedent, consequent
- Running assertions using questasim, debugging the assertions in waveform
- Assertion hierarchy – property, sequence, boolean expression
- ##, |-> and |=> operators
- Assertion examples for clock frequency check
- Assertion with local variables
- Assertions for simple timing diagrams
- Listing down and implmeneting assertions for simple designs – Async FIFO, Interrupt controller
- DPI
- Direct Programming Interface(DPI)
- import and export of functions
- Configuration libraries, Packages, XMR
- Configuration Libraries
- Incremental compilation
- Packages – defining, importing
- XMR
- Configuration libraries, Packages, XMR
- Compiler directives & Macros
- Parameterizable macros
- VCD – value change dump
- common array methods
- Callbacks – multiple use case examples
- What is UVM? Need for a methodology?
- How UVM evolved?
- OVM, AVM, RVM, NVM, eRM
- UVM class library
- Classification of base classes in various categories
- OOP basics
- Encapsulation
- Inheritance
- Polymorphism
- Parameterized classes
- Parameterized macros
- Static properties and static methods
- Abstract classes
- Pure virtual methods
- How above aspect correlates with UVM implementation.
- UVM Class Library, Macros, Utilities
- Detailed overview of important UVM base classes, Macros and Utility classes.
- UVM TB Architecture
- Setting up a UVM based testbench for APB protocol from scratch.
- Significance of uvm_root in UVM based testbenches.
- run_test, how it starts whole TB flow.
- Command line processor
- Reporting classes
- Uvm_report_object
- Uvm_report_handler
- Uvm_report_server
- Detailed examples on use of methods in these classes.
- Objections
- UVM Factory
- Configuration DB, Resource DB
- Detailed usage of both data bases.
- How config_db is related to resource_db?
- Using config_db to change the testbench architecture.
- TLM1.0
- Push
- Pull
- FIFO
- Analysis
- Complex example on AHB to AXI transaction conversion.
- Simulation Phases
- UVM common phases
- Scheduled phases
- Sequences, Sequencers
- Default sequence
- p_sequencer
- m_sequencer
- Test case development
- Different styles of mapping testcase to sequence
- Using default sequence and scheduled phases
- Using sequence start method
- Different styles of mapping testcase to sequence
- Configuring TB Environment
- Advanced aspects of developing a highly configurable test bench environment.
- Concept of knobs of test case scenario generation
- Using top level parameters to control the overall TB architecture
- Different testbench component coding
- Monitor
- Coverage
- Scoreboard
- Checkers
- Assertions
- Different styles of sequence development
- `uvm_do
- Start_item and finish_item
- Using existing sequences
- Sequence library
- Creating complex test cases using sequence library
- Virtual Sequencer, Virtual sequences
- Installing Linux platform in Windows
- Linux basics
- Linux versus Windows
- Linux Terminal
- File and Directory management
- Changing file permissions
- Absolute path and relative path
- Working with directories
- GVIM – major keyboard shortcuts
- Text display commands
- Root configuration files
- Environment variables
- Text processing commands
- grep, fgrep
- xargs
- SEd
- AWK
- Pipes and filters
- Connecting to server
- Process management
- LSF
- Ping
- FTP
- CTAGs
- File compress and extract
- Soft links
- Protocol basics
- Protocol overview
- Protocol features
- AMBA protocol overview
- AXI Protocol basics
- SOC Architecture – Significance of AXI protocol
- AXI based system architecture
- Correlating AXI with APB protocol
- Ports(signals) required for AXI protocol
- AXI Channels
- Write & Read Channels
- Handshaking using valid and ready
- Write Channel Signals – Address, Data and Response
- Read Channel Signals – Address and Data
- Timing diagrams
- How to draw the timing diagrams?
- Write Transaction Timing Diagram
- Read Transaction Timing Diagram
- AXI transaction analysis for big endian and little endian architecture
- Wrap transactions – write and read
- Narrow transfers
- Data bus and strobe relation
- Aligned and unaligned transfers
- AXI signal encoding
- Responses in AXI
- Locked and exclusive transfers
- Overlapping, out of order, interleaved txs
- Interconnect role in out of order transaction
- Significance of ID in AXI protocol
- AXI Channel handshake dependency
- Cacheable and bufferable transactions
- Protected transactions
- AXI VIP and UVC development
- Need for UVC?
- Different types of UVC’s
- UVC usage in module and SOC verification
- Where Passive UVC are used?
- UVC integration in to TB
- AXI UVC architecture
- AXI Transaction Definition
- AXI UVC coding
- AXI TB simulation and wave form analysis
- AXI UVC integration
- AXI scoreboard coding
- SoC Verification Concepts
- Module Level Verification
- Constrained Random Verification
- Coverage Driven Verification
- Directed Verification
- Assertion Based Verification
- Schematic tracing
- RTL tracing
- FIxing RTL and TB syntax and logical errors
- SOC Architecture overview
- SOC verification concepts
- SOC Components
- SOC use cases
- SOC Testbench architecture
- SOC verification differences with module verification
- Specification
- RTL coding, lint checks
- RTL integration
- Connectivity checks
- Functional Verification
- Synthesis & STA
- Gate level simulations
- Power aware simulations
- Placement and Routing
- DFT
- Custom layout
- Post silicon validation
- Python Interpreter
- Variables
- File management
- Subroutines
- Regular expressions
- Object oriented Python
- Python modules
- Facing interviews effectively
- industry work culture
- Group discussions
100+ detailed assignments covering all aspects from Verilog, Advanced digital design, System verilog, UVM, AXI protocol, VIP Development, Ethernet MAC core verification, RTL debug, UNIX and PERL scripting.
Course Overview
There are two kinds of internships.
One, You join a company where they will give you a junk work which their permanent staff don’t want to do. They will pay you some stipend for doing the same. It doesn’t offer any significant learning.
Second, you join internship where you learn new languages, protocols and skillset which you don’t learn as part of college curriculum.
We offer internship in 2nd category, where student gets to learn new skill set, which improves the candidate employability for current job requirements.
Student can pursue internship and project on any of the VLSI domains including RTL design, functional verification, Physical design, DFT, STA, and custom layout.
One year time spent on MTech project gives ample time to the student to work on complex projects inline with industry requirements. It helps student improve the resume and overall skillset, ultimately helping in getting a right job.
- Projects on IEEE standard
- Projects based on industry standard Protocols like AXI, AHB, USB, PCIe etc
- 1 year experience letter on completion of internship
Projects
- Course divided in to 2 aspects
- Learning phase
- Application phase
- During ‘learning phase’; Student will undergo 6 months extensive training on Advanced Digital Design, Verilog, SystemVerilog and UVM basics, standard protocols like AXI, AHB, Ethernet MAC, etc. Student will be working on multiple industry standard project as part of SV & UVM learning.
- During ‘application phase’, Student will be working on industry standard project with trainer guidance. Same project can be used as MTech Project.
- Verification IP Development for AXI3.0 protocol using SV
- Memory verification using test bench with configurable number of agents
- RTL coding of Synchronous & Asynchronous FIFO and verification using UVM
- Design and verification of SPI Controller
- Design and verification of Interrupt controller
- Design and verification memory with front door and back door access
- Design & verification of PISO and SIPO using Verilog
- CRC calculation logic using standard CRC polynomials
- Clock generation for a user provided frequency, duty cycle and jitter
- RTL coding and verification of Dynamic pattern detector and overlapping & non-overlapping pattern detector
- RTL coding and verification of Dual port RAM
- Parameterizable full adder
- AXI2OCP Bridge Design Functional Verification
- Ethernet MAC Design Functional Verification
- AXI Interconnect Design Functional Verification
- AHB Interconnect Design Functional Verification
- AHB2AXI Bridge Design Functional Verification
- UART Controller Design Functional Verification
- PRCM Design Functional Verification
- DMA Controller Design Functional Verification
- USB2.0 core verification
- PCIe TL VIP Development
- PCIe DLL VIP Development
- PCIe PL VIP Development
Schedule
| Course | MTech project and internship |
|---|---|
| Duration | 10 months or 1 year |
| Next Batch | Student can join any time as per their convenience |
| Mode of training | Classroom training & Live online training Course can also be done in hybrid mode. |
| Batch Size | 20 |
Demo
FAQs
- Course presentations for all topics
- Session notes
- Lab documents with detailed steps
- User guides
No per-requisites. Good to know C language & exposure to Digital Design concepts
- Each aspect of course is supported by lot of practical examples
- Dedicated full day lab sessions to ensure student does complete testbench development from scratch
- Yes, You will have option to view the recorded videos of course for the sessions missed
- You will have option to repeat the course any time in next 1 year
- Yes, Course fee also includes support for doubt clarification sessions even after course completion
- You have option to mail you queries
- Option to meet in person to clarify doubts
Trainer
Experienced Trainer
- 10+ years of rich experience of working in Functional Verification domain across various mobile, networking, high speed peripheral domains.
- Experience of working on functional verification of Multiple Complex SOCs, multiple Sub systems
- Experience of working on multiple complex module level projects
Certificate
Play Video
- 1-1 Dedicated Mentor Support
- 24/7 Tool Access
- Multiple mock interviews
- Industry Standard Projects
- Resume Preparation