Syllabus
Course Overview
Demo Video
Schedule
FAQs
Trainer
Syllabus
- CXL introduction
- CXL
- Flex Bus
- CXL system architecture
- CXL Type 1, Type 2 and Type 3 devices
- Multi logical device
- CXL device scaling
- CXL fabric
- G-FAM type3 device
- CXL transaction layer
- io, CXL.cache, CXL.mem
- Transaction ordering summary
- Transaction flows to device attached memory
- CXL Link layers
- io Link Layer
- cache and CXL.mem 68B Flit Mode Common Link Layer
- cachemem Link Layer 256B Flit Mode
- CXL ARB/MUX
- vLSM states
- ARB/MUX Link Management Packets
- Arbitration and Data Multiplexing/Demultiplexing
- Flex Bus Physical Layer
- Flex Bus.CXL Framing and Packet Layout
- 256B Flit Mode Retry Buffers
- Link Training
- 68B Flit Mode: Recovery.Idle and Config.Idle Transitions to L0
- L1 Abort Scenario
- 68B Flit Mode: Exit from Recovery
- Retimers and Low Latency Mode
- Switching
- Switch configuration and composition
- io, CXL.cachemem Decode and Forwarding
- CXL Switch PM
- CXL Switch RAS
- Fabric Manager Application Programming Interface
- CXL fabric architecture
- Control and status registers
- Configuration space registers
- Memory mapped registers
- Reset, Initialization, configuration and manageability
- CXL Boot and Reset Overview
- CXL Device Boot Flow
- CXL System Reset Entry Flow
- CXL Device Sleep State Entry Flow
- Function Level Reset (FLR)
- Cache Management
- CXL Reset, Hot-Plug
- Software Enumeration
- RCD Enumeration
- Power management
- CXL power management
- io Link power management
- CXL security
- CXL IDE overview
- io IDE
- cachemem IDE
- Reliability, Availability and Serviceability
- CXL error handling
- CXL error injection
- CXL viral handling
- Performance considerations
- Performance monitoring
Course Overview
Course Overview
CXL training is a 6 weeks training covering all the aspects starting from CXL system architecture, transaction layer, link layer, arbitration, multiplexing, flex bus physical layer,
switching, register and reset, initialization, configuration, etc.
Course also focus on power management, security, performance, etc.
Demo Video
Demo Videos
Schedule
| Course | CXL training |
|---|---|
| Duration | Live training : 6 weeks eLearning : 36 hours |
| Next Batch | |
| Schedule | Saturday, Sunday, 10AM to 1:30PM |
| Tool | This is protocol only training |
| Mode of training | Live training for minimum of 10 participants or corporate training eLearning with dedicated mentor for doubt clarifications |
| Fee | Fee: eLearning : INR 9K + GST Live training: INR 12K + GST |
| Assignments | 5 |
FAQs
- Course presentations for all topics
- Session notes
- Lab documents with detailed steps
- User guides
- Exposure to standard bus protocols
- Exposure to Testbench component coding using SystemVerilog
Each session of course is recorded, missed session videos will be s
- Yes, You will have option to view the recorded videos of course for the sessions missed
- You will have option to repeat the course any time in next 1 year
- Yes, Course fee also includes support for doubt clarification sessions even after course completion
- You have option to mail you queries
- Option to meet in person to clarify doubts
Trainer
Experienced Trainer
- 12 years of work experience in Functional Verification domain across various mobile, networking, high speed peripheral domains.
- Experience of working on functional verification of Multiple Complex SOCs, multiple Sub systems
- Experience of working on multiple complex module level projects
Play Video
- 1-1 Dedicated Mentor Support
- mock interview
- Support with resume update