What student learns from this project:
- Understand various 802 standards and more specifically 802.3 standard
- Understand various layers in OSI reference model and significance of network layer and MAC layer.
- Understand the whole process of functional verification flow starting from Specification to coverage analysis and closure.
- Specification detailed overview
- Reading design specification
- Listing down features, scenarios
- Developing test plan
- Test bench architecture
- Test bench component coding
- Functional coverage coding
- Register model coding and integration
- Assertion development
- Test bench component integration
- Sanity Testcase coding
- Register access test cases
- Register write-read test
- Register reset test
- Front door and back door access tests using register model
- Register test debug
- Functional Testcase coding
- Scoreboard implementation
- Updating scoreboard with register model predict
- Regression setup using Python
- Regression debug
- coverage report generation and analysis
- Functional and code coverage analysis
Course Overview
Ethernet MAC is MAC core with transmit and receive logic working at 100Mbps. Design consists of five sub modules including DMA controller, MII, transmit, receive and control module. Course also covers the MAC 802.3 protocol standard.
This project provides student with detailed exposure to complete functional verification flow starting from reading the specification till coverage report generation and regression analysis. Student will get exposure to regression setup, coverage analysis and scoreboard development.
This project is also good for working professionals whose work is generally confined to limited aspects of verification flow and want to get quick hands on exposure to complete flow.
| Course | Ethernet MAC 100Mbps core verification using SV & UVM |
|---|---|
| Duration | Live training : 5 weeks eLearning : 35 hours |
| Next Batch | 18/March |
| Mode of Training | Live training for a minimum of 10 pax or corporate training eLearning course with dedicated doubt clarification sessions |
| Tool access | 5 weeks |
| Fee | Live training : INR 11,000 + GST eLearning : INR 9,000 + GST |
- Course presentations for all topics
- Session notes
- Lab documents with detailed steps
- User guides
- Exposure to standard bus protocols
- Exposure to Testbench component coding using SystemVerilog
- Yes, trainer will be accessible over phone and email for doubt clarification.
- Typically you can expect response within 4 hours.
- Yes, Course fee also includes support for doubt clarification sessions even after course completion
- You have option to mail you queries
- Option to meet in person to clarify doubts
- 10+ years of rich experience of working in Functional Verification domain across various mobile, networking, high speed peripheral domains.
- Experience of working on functional verification of Multiple Complex SOCs, multiple Sub systems
- Experience of working on multiple complex module level projects
- 1-1 Dedicated Mentor Support
- 24/7 Tool Access
- Mock Interview
- Industry Standard Projects
- Support with resume update