GLS Training

What is GLS?
- GLS basics and terminology
- GLS challenges
- Netlist
When GLS is run in ASIC flow?
Why we do GLS?
- Synthesis and STA basics
- How GLS differs from STA?
- Formal or LEC checks
- How GLS is run?
- Setting up GLS Test bench
- Force files
- GLS Test plan development
- Unit delay simulations
- Timing simulations
- GLS Frequency corners & timing modes, significance
- Understanding SDF contents
- SDF annotation
GLS : Good practices
- Synchronizer flop forces
- Command line options
- Dump hierarchies
- Proper SDF mapping
- No timing checks
- Choosing right frequency
- Force files
Debugging GLS failures
- Log file debug
- Adding optimal number of signals to waveform
- X tracing
- Data flow and Schematic tracing
Common GLS issues
- Test hanging
Debug tools
- Verdi
GLS advanced aspects
- ECO
SOC GLS debug concepts
- Two GLS hands on projects
- Setting up test bench
- Unit delay simulations
- Timing simulations
- Debug
GLS regression and signoff

Course Overview

Gate level simulations is an important aspect of VLSI design flow. It helps validate the gate level netlist for setup and hold time violations and any reset or power up sequence issues.

There is lot of motivation for running GLS even while STA is leveraging timing checks to major extent. GLS course will focus on teaching all the aspects of GLS from setup, test plan, frequency plans, SDF corners, and non-timing simulations. Course will also focus on various issues faced during GLS and debugging those.

Course involves two hands on projects using complex gate level netlist.

Course	Gate level simulations Training
Duration	Live training : 3 weeks eLearning : 25 hours
Next Batch
Schedule	Saturday, Sunday, 9AM to 1PM
Tool	Questasim, VCS
Mode of training	Live training for minimum of 10 participants or corporate training. eLearning with dedicated mentor for doubt clarifications.
Fee	Live training : INR 8K + GST eLearning : INR 7K + GST

Course materials shared

Course presentations for all topics
Session notes
Lab documents with detailed steps
User guides

What are the Course Prerequisites?

Expertise on digital design concepts
Exposure to Testbench & testcase development using Verilog/SystemVerilog

What if I miss few sessions during course?

Each session of course is recorded, missed session videos will be shared

Course has started few weeks back, can I still join the course in between?

Yes, You will have option to view the recorded videos of course for the sessions missed
You will have option to repeat the course any time in next 1 year

Do you offer support after course completion?

Yes, Course fee also includes support for doubt clarification sessions even after course completion
You have option to mail you queries
Option to meet in person to clarify doubts

Experienced Trainer

10+ years of rich experience of working in Functional Verification domain across various mobile, networking, high speed peripheral domains.
Experience of working on functional verification of Multiple Complex SOCs, multiple Sub systems
Experience of working on multiple complex module level projects