PCIe topology, configuration headers, enumeration |
3 |
Address space, transaction routing |
2 |
Transaction layer – TLP types, header fields, flow control, QOS, VC/TC mapping |
5 |
Data link layer – DLLP types, significance, Flow control, VC initialization, ACK/NAK protocol, Packet retry |
5 |
Physical layer – Logical sub block, 128b/130b encoding, scrambling, LTSSM |
5 |
Physical layer – Electrical sub block, PIPE, SerDes, Transmit and received paths |
3 |
PCIe test plan development |
2 |
Total |
35 |