- Overview
- Env Setup
- Special Variables
- Data Types
- Variables
- Operators
- Decisions
- Loops
- Arrays, Strings, Lists, Dictionary
- History and Redoing of commands
- String Pattern Matching commands
- Working with files – open, write, read, append
- Regular expressions
- Parsing VHDL code to Verilog code
- Lab 1: Scripts related to file Operations
- Lab 2 : Execution of redirect commands
- Lab 3 : Execution of Control Flow, Maths Functions.
- Lab 4 : Writing own Procedural commands.
- Lab 5: Writing own Procedures with positional arguments
- Lab 6 : Writing own Procedures with non-positional arguments.
- Lab 7 : Commands to handles design objects
- Lab 8 : Commands to handle Collections
- Lab 9 : Scripts on collections and its attributes
- Lab 10: Scripts on linking design objects with another design objects.
- Lab 11 : Scripts on filtering applications on design objects
- Lab 12: Script to get gate count of full chip.
- Lab 13: Script for macro placement.
- Lab 14: Script for finding high fan out nets
- Lab 15: Script on ECO fixing like inserting buffers on high fan out nets
- Lab 16: Script on inserting antenna diodes to fix antenna violations.
- Lab 17: Script for port placement based on given co-ordinates or location
- Lab 18: Script for Upsizing driver for DRV violated net
- Lab 19: Script for inserting buffer for DRV violated net
- Lab 20: Script for getting common instance in most violated paths
- Lab 21: Script for Extracting Start point and end point from violated timing paths
- Lab22: Script for filtering Arrival time and Required time from violated paths
- Lab23: Proc for cloning to split fanout of a net
- Lab24: Script to filter warning and error messages in log files
- Lab25: Script to plan and create voltage area for multi-voltage design
- Script to write customize pin placement.
- Script to write TCL file to execute some set of command from the collection (it can be a file or variable).
- Script to find shorted (nets having shorts) nets.
- Script to improve the routing of bad nets.
- Script to insert buffer to all endpoints having hold violations.
- Script to resolve overlapping even after legalize placement.
- Script for handling logs from different Synopsys tools.
- Script to report endpoints and start points slack of top 1000 failing paths
- Script to get a list of the register sinks for a clock
- Script to return all the instance pins that are in timing path.
- Script to report slack and difference between clock arrival time at launch and capture clocks.
- Script to report logics between reg to reg path. This script can be modified for different path groups.
- Script to find the number of logic levels(combinational) in a timing path or group of timing paths.
- Script to report worst slack for all clock group.
- Dedicated projects based on audience requirements
- Assignments based on TCL flow automation for various aspects of VLSI backend flow.
Application Oriented TCL for Synopsys
TCL training is for VLSI professionals and students who work on Synopsys tools like ICC/ICC2 Compiler, DFT Compiler, Design Compiler , Primetime. Training will enhance your scripting skills which increase your productivity while using Synopsys tools. Real time Projects/Assignments will be given to audience as well as driven by audience requirements. Explanation and Execution of all concepts, commands and scripts will done in ICC shell to connect to audience requirements. VPN will be given to audience for practice and execution of projects/assignments.
Tools Used for TCL Scripting : ICC2, Primetime, Design Compiler
All the EDA tool flows from Synopsys, Cadence and Mentor Graphics use Tcl as the primary scripting interface for their flows. TCL as a single command language in all EDA tool flows ensures that a designer only needs to learn Tcl in order to work with all the flows.
TCL scripting is much sought after skill set for every VLSI engineer. Training will provide the detailed practical exposure on each aspect of project flow setup mostly focused on Physical Design, STA, and functional verification with multiple hands on examples.
| Course | TCL scripting – Deep dive |
|---|---|
| Duration | Live training : 6 weeks eLearning : 40 hours |
| Next Batch | |
| Schedule | |
| Freshers | 6 days/week, 4 hours/day |
| Working professionals | Saturday & Sunday(9AM – 1PM IST) Access to all course recorded videos for entire course duration |
| Tool | ICC II, PT |
| Mode of training | Classroom training & Live online training Course can also be done in hybrid mode. |
| eLearning with dedicated mentor for doubt clarifications. | |
| Fee | Live training : INR 9K + GST eLearning : INR 7.5K + GST |
- Course presentations for all topics
- Session notes
- Lab documents with detailed steps
- User guides
- Yes, You will have option to view the recorded videos of course for the sessions missed
- You will have option to repeat the course any time in next 1 year
- Yes, Course fee also includes support for doubt clarification sessions even after course completion
- You have option to mail you queries
- Option to meet in person to clarify doubts
Experienced Trainer
- 8 years of rich experience of implementing EDA flow using PERL, TCL, SHELL and PYTHON.
- Every engineer who wants to utilize scripting to get smarter with work. Ex: A work manually done for 3-4 hours, could be done in 10-15 mins using intelligent scripting.
- Every engineer who has repetitive work on daily basis, and would like to automate the same. Time can be better utilized on learning more interesting things.
- Engineering college faculty looking to enhance their VLSI skill set
- 1-1 Dedicated Mentor Support
- 24/7 Tool Access
- mock interview
- Industry Standard Projects
- Support with resume update