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VLSIguru top training institute in Bangalore

Course content

  • Scan Insertion, need of scan insertion, scan DRCs, clearing Scan DRCs.
  • Scan Compression, need of scan compression, EDT architecture, deciding no. of internal chains and external channels.
  • Need of ATPG, fault simulation, fault classes, fault categories, fault models (SA, TDF, IDDQ, PDF), On-chip Clock Controller (OCC), different types of patterns, coverage analysis and improvement.
  • Simulations, it’s need and simulation mismatch debug.
  • JTAG, it’s need, TAP architecture, JTAG FSM, Boundary Scan.
  • IJTAG architecture, advantage of IJTAG over JTAG
  • Memory faults, algorithms, Tessent MBIST implementation and Architecture.
  • Hierarchical Scan, Scan Wrappers.

 

VLSIguru top training institute in Bangalore
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