RTL Design and Integration training is a 3.5 months course focused on all the aspects of RTL integration job role including Linting, CDC, manual integration, UPF, SDC, Synthesis, LEC and STA with multiple hands on projects.
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RTL Design and Integration Course Overview
Course Overview
RTL Design and Integration training is a 3.5 months course focused on all the aspects of RTL integration job role including Linting, CDC, manual integration, UPF, SDC, Synthesis, LEC and STA with multiple hands on projects.
Training focus will be on manual integration, developing the glue logic during integration, tool based integration, linting, CDC, UPF, Synthesis and STA.
Like any other job role in VLSI design flow, RTL integration is also a tool intensive job. RTL Integration course will provide the student with expertise on Synopsys Spyglass(Lint and CDC), Design compiler for Synthesis and Primetime for STA. Tools helps with quick turn around in time critical projects, where integration engineer is expected to release the design tag in short timelines.
With growing design complexity and reducing timelines, it requires efficient techniques for RTL connectivity and developing the logic for various blocks integration. LINTING is a static analysis of the RTL code based on some set of rules and guidelines. When these rules or guidelines are broken, LINT tool flags errors or warnings, which need to be reviewed, fixed or waived by designer. This course discusses good amount of LINT rules and guidelines, which will enable audience to gain good design practices and perform LINTING if needed.
Course includes Splyglass based CDC(Clock domain crossing) for the synchronization of various signals moving across one clock domain to another. Course will focus on in-depth analysis of Lint and CDC checks with hands on integration project.
Similar to how we have multiple clocks in a System-On-Chip design we do have multiple power domains being used in modern SOCs for different reasons. Unified Power Format is IEEE standard developed by Accellera. This is used to ease the job of specifying, simulating and verifying the design with multiple power states and power islands.
UPF is designed to specify power intent of a design at high level. UPF scripts mention the details of which power rails need to be connected to which IP, whether the register values need to be retained during power off, whether we need an isolation of design in case of power down and manages voltage levels shift as signals cross from one power domain to the other. In this course we discuss the need for multiple power domains, basics of UPF and some examples.
Spyglass, RTL integration tools, VLCP, Design compiler, Primetime, Formality
Key Features
Who All Can Attend This RTL Design and Integration Course?
The RTL Design and Integration Course can be attended byPre-requisites To Take RTL Design and Integration
- Basic understanding of digital logic design concepts.
- Familiarity with at least one hardware description language (Verilog/VHDL).
- Fundamental knowledge of semiconductor devices and CMOS technology.
High Demand for RTL Design and Integration
Know about the Growing VLSI industry
RTL Design Engineers are in high demand as the semiconductor industry expands, with projections showing a significant increase in VLSI design roles globally. They are crucial for creating the foundational hardware descriptions for complex chips.
₹4 LPA
₹8 LPA
₹10 LPA
₹20 LPA
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Explore a wide range of VLSI and Embedded Systems courses to get industry-ready.
50+ industry oriented courses offered.
