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Advanced Custom and analog layout training is a 5 months course with multiple hands on projects done using both SYNOPSYS Custom compiler and Cadence Virtuoso at 18nm technology node. The course is designed for working professionals planning to pursue career in custom and analog layout or those who wants to learn advanced aspects of Custom and analog layout.
Course Overview
Advanced Custom and Analog Layout Training – Summary
Duration: 5 months advanced program
Tools:SYNOPSYS Custom Compiler and Cadance Virtuoso (24×7 Tool access)
Placement Support: Institute provides placement support till candidate gets a JOB
Training Highlights:
Focused training for working professionals aiming for roles in Custom/Analog Layout Design
Coverage of Analog, Memory, Standard Cell, and IO Layouts
Hands-on experience with real-world layout design challenges
Technical Coverage:
Layout Fundamentals and Hands-on Standard Cell Layouts
IO Layout and Memory Layout for various architectures
Detailed Analog Layout techniques and industry practices
Mismatches & Matching, Noises & Coupling mechanisms
Failure Mechanisms: Electromigration, IR Drop, LOD & Stress, WPE, Antenna Effects, Latch-Up, ESD
Hands-on Training:
20+ Labs and Assignments covering entire layout design process
Multiple projects on advanced analog layout challenges
Concepts like Common Centroid, Interdigitation, Resistor/Capacitor Matching
OpAmp Circuits, Current Mirrors, PLLs, ADCs, DACs, Bandgap Reference Design
Design of Temperature Sensors, Bias Circuits (Current & Voltage), Large Drivers
LNA, Mixers, Sense Amplifier, and Bit Cell Layouts
Training Delivery:
Conceptual clarity with real-time examples and interactive sessions
Guided by experienced professionals with industry layout background
Program Highlights:
Designed for professionals looking to specialize in Analog & Custom Layout
Realistic project-based training for layout problem solving
Exposure to industry best practices and ESD/failure mechanism considerations
Institute Info:
Offered by VLSIGuru, established in 2012
Trained over 10,000+ students
Affordable in-class training in Bangalore
Online training available for students outside Bangalore
Detailed overview:
Advanced Custom and analog layout training is a 5 months course targeted for working professional planning to pursue career as a layout design engineer or wants to learn advanced aspects of Custom and analog layout. Training focused on all the aspects of layout including Analog layout, Memory layout, Standard cell layout and IO layout.
Course also includes detailed sessions on layout basics, hands on standard cell layouts, IO layout and memory layout for different architectures. Followed by various analog layout techniques with detailed discussion on Mismatches & Matching, Noises & Coupling, various failure mechanisms which includes Electro migration, IR drop, LOD & Stress effects, WPE, Antenna Effects, Latch up, ESD. Course includes 20+ detailed labs & assignments covering all aspects of custom layout with multiple hands on projects.
Analog layout techniques will involve multiple hands on projects covering various concepts such as common centroid, inter digitation, resistor matching, capacitor matching and opamp circuits, current mirrors, PLL’s, ADC’s, DAC’s, Bandgap, Temperature sensors & Biases -> Current & Voltage bias lines, Large drivers, LNA & Mixers, and Sense amplifier & Bit cell development.
Layout Editor Tool
Understanding the schematic symbols and parameters
Creating and managing libraries and cell
Commands for Layout editing.
Commands for schematic editing.
Verification : DRC and LVS
Antenna effect, latchup, Electromigration, IR Drop
Analog Layout of OpAmp, Current Mirror, PLL, ADC, and DAC
Resistor, Capacitor layout techniques
CMOS and BiCMOS layout techniques
Standard Cell Layout : Inverter, AND, OR, NAND, NOR, AOI, OAI, Latches, and Flop
Schematic entry
Early parasitics
Estimated parasitic assistant
Reliability analysis
Static circuit checks(CCK)
Pre-layout simulation and analysis
Standard cells
Analog circuits
Analog and mixed mode circuits
Layout
Analog and Digital co-design
Fusion compiler co-design
IC Compiler II co-design
IC Compiler co-design
In-design error checks
DRD
IC Validator live DRC
Via checks
Metal Density analysis
Color decomposition
In-design electrical checks
Electro migration
Resistance
Capacitance
Shield coverage
Voltage annotation for VDRC
Early parasitics
Estimated parasitic assistance
Partial layout extraction
Power device design
Power device designing
Analog design migration
Schematic migration
Layout migration
Mismatches and Matching
Techniques
Inter digitization
Common centroid
Failure Mechanism
Electro migration
IR drop
LOD & Stress effects
WPE, Antenna Effects
Latch up
ESD
High voltage rules
EOS effects
Noises & Coupling
Different Types of process
Advantages & Disadvantages of below
Planar CMOS
FD-SOI
SOI
Bi-CMOS
Gallium Arsenide
Silicon-Germanium
Finfet
Full Chip Construction
Scribe Seal
Pad Frame
Integration and guidelines
Packaging
Std Cell & Memories.
IO Layout Guidelines : High speed IOs and High Speed Interfaces.
Sense amplifier & Bit cell development
Why memory layout different than analog layout
Memory layout flow
Types of memory layout (SRAM/DRAM/ROM)
Introduction to SRAM memory layout
Fixing few manually created leaf-cell errors which impact
Abutment issues
Impact of IR, EM and DFM .
SRAM memory design architecture
Words line and address line
SRAM rows and column design
Building blocks of SRAM
Memory Bit cell
Row decoder
Word line driver
Sense amplifier
Control block
Misc digital logic.
Pitch Calculation for blocks.
Power Planning
High speed Analog Layout
RF Layout guidelines with Transmission lines and inductor concepts
Handling clocks
Analog Circuits & Layout guidelines
Single & Multi stage differential op amp layout
current mirror layout
PLL, DLL and Oscillators
LDO and other regulators
ADCs & DACs
Bandgap, Temperature sensors & Biases -> Current & Voltage bias lines
Large drivers
input pair, differential routing, Power routing, offset minimising
Power/Signal IR Drop
cross-talk and coupling
Electrostatic Discharge
Deep Submicron Layout Issues
Shallow Trench Isolation (LOD)
Well Proximity Effect
Design Rule Checks
Layout Versus Schematic (LVS)
Electrical Rule Checks (ERC)
Antenna Checks
Latch-up
Reliability checks like EM and IR analysis
Design for manufacturability (DFM)checks
Electrostatic discharge (ESD) path checks
Assignments and multiple hands on projects
Best Practices & Interview Questions.

DFT Engineers with hands-on skills in scan insertion, ATPG, MBIST, and JTAG are highly sought after. Experience with Synopsys and Tessent tools significantly boosts job prospects and compensation. Bangalore, Hyderabad, and Noida are top-paying hubs.
₹8 LPA
₹12 LPA
₹16 LPA
₹20 LPA
₹28 LPA




This advanced program is crucial for working professionals aiming to specialize in Custom and Analog Layout Design. It offers focused training covering Analog, Memory, Standard Cell, and IO layouts with hands-on experience. You'll tackle real-world challenges, understand critical failure mechanisms like ESD and electromigration, and gain proficiency through 20+ labs and multiple advanced analog layout projects, enhancing your career prospects.

At VLSIGuru, we believe that education should lead to meaningful employment. Our training programs are designed not just to impart technical excellence, but also to bridge the gap between academic learning and industry demands. With a strong network of hiring partners and a proven track record, we ensure that our students are career-ready.
Placement Highlights

At VLSIGURU, we provide industry-focused VLSI training and guidance that helps students and professionals build strong technical skills and succeed in their careers. Our programs are designed to be practical, flexible, and aligned with current industry requirements.




You will master critical skills in areas like mismatch and matching techniques, noise coupling reduction, and layout for high-performance analog circuits.
Absolutely! Our comprehensive curriculum covers the fundamentals and advanced techniques applicable to various specialized layout domains.
Our course includes specific interview preparation sessions covering key concepts and problem-solving relevant to custom layout roles.
VLSI Guru provides dedicated placement assistance, leveraging our industry connections to help you secure advanced custom layout positions.
Yes, our curriculum includes multiple hands-on projects based on realistic industry challenges and complex analog layout scenarios.
Our intensive advanced layout training program is a focused 4.5-month course designed for working professionals.
VLSI Guru's training provides a strong foundation and insights into continuous learning resources within the VLSI layout community.
We provide guidance on creating clear and comprehensive documentation, essential for collaboration and future reference in your professional work.
Our practical sessions emphasize understanding potential issues and developing effective strategies for debugging and resolving unexpected behavior.
We incorporate discussions on the latest trends like FinFET layout and considerations for advanced technology nodes in our curriculum.
You'll gain in-depth experience with industry-leading EDA tools, including their advanced features for layout, simulation, and verification.
The training covers systematic debugging techniques and best practices for identifying and resolving complex layout-related problems effectively.
We explore various implementation methodologies using industry-standard tools like Synopsys Custom Compiler and Cadence Virtuoso for diverse circuit types.
Advanced layout tackles complex issues like mismatch, noise, and failure mechanisms, optimizing for performance and reliability in cutting-edge designs, which we thoroughly cover.
VLSI Guru offers comprehensive course materials, 24x7 tool access, and guidance from industry experts, making us your primary resource.
We provide dedicated interview preparation sessions focusing on common questions, problem-solving, and best practices in custom layout scenarios.
Our course clearly distinguishes its unique design rules, optimization goals, and area/performance trade-offs with specific modules and examples.
You'll gain hands-on experience applying advanced techniques like common centroid and interdigitation through practical labs directly relevant to your projects.