Synthesis and STA Training is a 4-month industry-focused program that provides participants with in-depth exposure to Synthesis methodologies and Static Timing Analysis (STA) for successful and confident tape-out of semiconductor designs. This course is designed to equip engineers with the skills required to handle real-world challenges in ASIC design, timing closure, and sign-off strategies for advanced technology nodes (28nm to 5nm).

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STA Training Overview

Static Timing Analysis (STA) is at the core of digital design sign-off, ensuring reliable performance and timing closure before fabrication. This training covers:

• Fundamentals of setup and hold time fixing

• Timing constraint development for complex SoC designs

• Transition times, PVT variations, crosstalk noise and delay

• Advanced OCV and path-based vs. graph-based analysis

• Clock path and data path ECOs for timing closure

• Multi-Mode Multi-Corner (MMMC) sign-off strategies

Participants will gain hands-on experience using industry tools (Synopsys PrimeTime) to analyze real designs, fix timing violations, and implement ECOs. The course also emphasizes sign-off quality analysis and advanced topics such as CPPR and pessimism removal techniques.

By the end of the STA module, candidates will have the expertise to perform block-level and full-chip STA, making them job-ready for Physical Design and Sign-Off roles.

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Synthesis Training Overview

The Synthesis Training module covers the entire flow of converting RTL to gate-level netlists, applying constraints, optimizing designs, and preparing hand-off databases for physical design (PnR). Key topics include:

• RTL design constructs and elaboration

• Generic and technology-mapped synthesis

• Constraint development using SDC

• Design optimization techniques for area, power, and timing

• Scan insertion and DFT considerations

• Logical Equivalence Checking (LEC)

• Hierarchical and topographical synthesis methods

Hands-on projects will be conducted using Cadence Genus/RTL Compiler for synthesis and Synopsys Design Compiler for validation.

By the end of this module, participants will be confident in performing RTL-to-GDSII hand-off, writing and debugging constraints, and ensuring timing-clean, power-optimized netlists.

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Key Learning Outcomes

• Master Synthesis and STA flow from RTL to sign-off

• Develop robust timing constraints (SDC) for real designs

• Fix setup and hold violations using ECOs

• Gain expertise in MMMC timing analysis

• Work on 2+ industry-standard sign-off projects with tool access (institute and remote VPN)

• Hands-on expertise with Synopsys Spyglass, Design Compiler, PrimeTime, and Cadence Genus

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Target Audience

• B.E/B.Tech, M.E/M.Tech graduates aiming to enter VLSI front-end design and sign-off roles

• Physical Design Engineers looking to strengthen their STA and synthesis skills

• Professionals seeking to transition into timing closure and design sign-off careers

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Course Topics

STA Training Topics

• Setup and hold timing checks

• Stage delay, cell delay & net delay

• Asynchronous flop recovery/removal

• Cross-clock and interface timing analysis

• Crosstalk delay & noise

• Advanced OCV and CPPR

• MMMC timing analysis

• Graph-based vs. path-based analysis

• ECO-based timing closure

• Constraint development and validation

Synthesis Training Topics

• RTL to gate-level netlist generation

• RTL constructs and elaboration

• DesignWare and logical operators

• Clock gating for power reduction

• Don’t-use/don’t-touch cells

• Scan insertion techniques

• Latch-based designs and time borrowing

• Multi-cycle and false path exceptions

• Hierarchical synthesis strategies

• Logical Equivalence Check (LEC) fundamentals

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This comprehensive program ensures that participants develop both theoretical expertise and hands-on tool skills, enabling them to confidently handle timing closure and synthesis challenges in modern VLSI design projects.