COURSE SCHEDULE - VLSI Guru

COURSE SCHEDULE (VLSI, EMBEDDED SYSTEMS)

GST is chargeable at 18% on top of the fee mentioned.
All Courses offered in
- Classroom training
- live online training
- Recorded videos for self paced learning
- 1-to-1 training(charged per hour basis)
There is option to join ongoing batch within 2 weeks from course start date, we help cover up the missed sessions. Beyond that student should join new batch.
Students joining Design verification, Physical Design, DFT and Custom layout courses, will have option to switch to any other course within 2 weeks of joining the course. There will not be any additional fee for switching to different course within 2 weeks.
Tool access for complete course duration for all relevant courses.

Courses	Start Date	Link
Functional verification interview training	Adhoc	Course Structure
Physical design interview training	Adhoc	Course Structure

Course	Course Details	Start Date	Course Duration	Fees	New Batch starts every
Functional Verification Training for Freshers	VLSI Course Structure	23/November	28 weeks	63000	5 weeks
Functional Verification Training for Experienced Engineers	VLSI Course Structure	04/November	22 weeks	50000	5 weeks
System Verilog Training	SV Course Structure	28/September	7 weeks	16000	5 weeks
MTech Internship in VLSI	MTech VLSI Internship Structure	23/November	10 months	63000	5 weeks
MTech Internship in Embedded systems	MTech Embedded systems internship Structure	Adhoc	10 months	63000	5 weeks
UVM Training	UVM Course Structure	05/October	8 weeks	19500	8 weeks
RTL Design and verification training	Course Structure	23/November	24 Weeks	63000	5 weeks
FPGA Design and verification training	Course Structure	23/November	24 Weeks	63000	5 weeks
Verilog Training	Verilog Course Structure	10/November	8 Weeks	15000	5 weeks
VHDL Training	VHDL Course Structure	Adhoc	5 Weeks	8000	Adhoc

Course	Course Details	Start Date	Course Duration	Fee	New Batch starts every
Physical Design Training	Course Structure	24/November	24 Weeks	63000	8 weeks
RedHawk (Power Integrity & IR Drop Analysis) Training	Course Structure	Adhoc	5 Weeks	17000	12 weeks
Synthesis and STA Training	Course Structure	Adhoc	12 Weeks	39000	8 weeks
DFT Training	course structure	23/November	24 Weeks	63000	8 weeks
Custom Layout & Physical Verification Training	Course structure	24/November	24 Weeks	63000	8 weeks

Course	Course Details	Start Date	Course Duration	Fees	New Batch starts every
Embedded Systems Training	Embedded Systems Course Structure	Adhoc	18 Weeks	39000	9 weeks

Ad Hoc below refers to, courses where we do not get frequent requests, and are offered only when
more than 5 students have registered for the course.

Course	Course Details	Start Date	Course Duration	Fees	New Batch starts every
ARM Training	ARM Architecture Training Course Structure	Adhoc	6 Weeks	19000	Adhoc
DDR Protocol Training	DDR Training Course Structure	Adhoc	6 Weeks	8000	Adhoc
PCIe Protocol Training	PCIe Training Course Structure	Adhoc	6 Weeks	11000	16 weeks
USB3.0 Protocol Training	USB30 Course Structure	Adhoc	6 Weeks	11000	16 weeks
GLS Training	GLS Course Structure	Adhoc	3 Weeks	7000	16 weeks
Low Power verification Training	Power aware verification course structure	Adhoc	3 Weeks	6000	Adhoc
USB2.0 protocol and USB2.0 core verification Training	USB2.0 Course Structure	Adhoc	7 Weeks	11000	Adhoc
AMBA(AXI, AHB, APB) protocol and VIP & UVC development Training	AMBA protocol training Course Structure	Adhoc	6 Weeks	15000	12 weeks
SoC Design & Verification Training	SoC Training	Adhoc	6 Weeks	15000	Adhoc

Course	Course Details	Start Date	Course Duration	Fee	New Batch starts every
PERL Training	PERL Course Structure	adhoc	5 Weeks	6000	10 weeks
Python Training	Python Course Structure	adhoc	5 Weeks	6000	10 weeks
TCL Training	TCL Course Structure	Adhoc	6 Weeks	9000	10 weeks
Shell Training	SHELL Course Structure	Adhoc	4 Weeks	4500	10 weeks

Call us for more details on VLSI Training course structure