COURSE SCHEDULE (VLSI, EMBEDDED SYSTEMS)

For all courses:

  • 18% GST applicable
  • All Courses offered in
  • Student can join ongoing batch within 2 weeks from course start date, we help cover up the missed sessions.
  • Students joining Design verification, Physical Design, DFT and Custom layout courses, will have option to switch to any other course within 2 months of joining the course with no additional fee.
VLSIguru quality traning affordable fee in Bangalore

Upcoming courses

Courses Start Date Link
Functional verification interview training Adhoc Course Structure
Physical design interview training Adhoc Course Structure

Courses in VLSI Front End domain

Course Start Date Course Duration Fee New Batch starts every
Functional Verification Training for Freshers 8/Feb 28 weeks 63000 5 weeks
Functional Verification Training for Experienced Engineers 8/Feb 22 weeks 50000 5 weeks
System Verilog Training 8/Feb 7 weeks 16000 5 weeks
MTech Internship in VLSI 8/Feb 10 months 63000 5 weeks
MTech Internship in Embedded systems Adhoc 10 months 63000 5 weeks
UVM Training 8/Feb 8 weeks 19500 8 weeks
RTL Design and verification training 8/Feb 24 Weeks 63000 5 weeks
FPGA Design and verification training 8/Feb 24 Weeks 63000 5 weeks
Verilog Training 8/Feb 8 Weeks 15000 5 weeks
VHDL Training Adhoc 5 Weeks 8000 Adhoc

Courses in VLSI Backend DOMAIN

Course Start Date Course Duration Fee New Batch starts every
Physical Design Training 9/Feb 24 Weeks 63000 8 weeks
RedHawk (Power Integrity & IR Drop Analysis) Training Adhoc 5 Weeks 9000
Synthesis and STA Training Adhoc 12 Weeks 39000 8 weeks
DFT Training 8/Feb 24 Weeks 63000 8 weeks
Custom Layout & Physical Verification Training 9/Feb 24 Weeks 63000 8 weeks

Courses in Embedded Systems

Course Start Date Course Duration Fees New Batch starts every
Embedded Systems Training Adhoc 18 Weeks 39000 9 weeks

Courses on SOC & Standard Protocols

  • Ad Hoc below refers to, courses where we do not get frequent requests, and are offered only when more than 5 students register for the course.
Course Start Date Course Duration Fees New Batch starts every
ARM Training Adhoc 6 Weeks 19000 Adhoc
DDR Protocol Adhoc 6 Weeks 8000 Adhoc
PCIe Gen5 protocol Adhoc 6 Weeks 11000 16 weeks
USB3.2 protocol Adhoc 6 Weeks 11000 16 weeks
Gate level simulations (GLS) Adhoc 3 Weeks 7000 16 weeks
Low Power verification Adhoc 3 Weeks 6000 Adhoc
USB2.0 protocol and USB2.0 core verification Adhoc 7 Weeks 11000 Adhoc
AMBA protocol and UVC development Adhoc 6 Weeks 15000 12 weeks
AMBA CHI Adhoc 6 Weeks 9000 6 weeks
ACE Protocol Adhoc 6 Weeks 4000 5 weeks
SoC Design & Verification Adhoc 6 Weeks 15000 Adhoc

Courses on Scripting Languages

Course Start Date Course Duration Fee New Batch starts every
PERL adhoc 5 Weeks 6000 10 weeks
Python adhoc 5 Weeks 6000 10 weeks
TCL Adhoc 6 Weeks 9000 10 weeks
Shell Adhoc 4 Weeks 4500 10 weeks

Call us for more details on VLSI Training course structure

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