Syllabus
Course Overview
Schedule
Demo
FAQs
Trainer
Syllabus
- USB2.0 overview
- LS, FS, HS
- USB topology
- components
- EHCI, UHCI, OHCI
- USB2.0 features
- USB reset
- Device detection
- Speed negotiation
- Enumeration
- Device descriptors
- Line states
- Data transfers
- USB core operation
- USB frame
- USB packets
- Token
- Data
- Handshake
- Special
- New packets in high speed
- USB transfer types
- Control transfers
- Interrupt transfers
- Isochronous transfers
- Bulk transfers
- Split transactions
- Reading USB2.0 core specification
- Feature and scenario listing down
- Test plan development
- Functional coverage point listing down
- Testbench architecture
- Testbench component coding
- Testbench integration
- Register listing down
- Register fields, attributes
- Developing register model in UVM
- Register model integration in to TB environment
- Sanity Test case coding
- Register access test case coding using register model
- Register reset test
- Register write read test
- Front door and back door access tests
- Test case debug
- Functional testcase coding
- Testcase debug
- Regression setup
- Report generation and coverage report analysis
- Functional coverage analysis
- Code coverage analysis
Course Overview
Course Overview
USB2.0 core is part of USB device, used to interface with USB function on one side and USB host on other side using UTMI. USB2.0 course includes detailed training on USB2.0 protocol including LS, FS and HS, with detailed understanding on frame, packet format.
USB2.0 core verification is done using SV and UVM starting from reading of specification, test bench setup, test case coding, regression set up and debug.
It is useful for working professionals to gain expertise on entire verification flow for a complex design.
Schedule
| Course | USB2.0 protocol and USB2.0 core verification using SV & UVM |
|---|---|
| Duration | Live training : 5 weeks eLearning : 35 hours |
| Next Batch | |
| Mode of Training | Live training for minimum of 10 participants e-learning for self paced learning |
| Fee | Live training : INR 10,000 +GST eLearning : INR 9,000 + GST |
| Certificate | Issued |
Demo
FAQs
- Course presentations for all topics
- Session notes
- Lab documents with detailed steps
- User guides
- Exposure to SV & UVM constructs.
- Exposure to setting up TB environment using SV & UVM
- Missed sessions will be backed up.
Trainer
- 12+ year’s exp. of working in functional verification with exposure to multiple SOC, Subsystem and module level verification projects.
- 1-1 Dedicated Mentor Support
- 24/7 Tool Access
- mock interview
- Industry Standard Projects
- Support with resume update