- Power Management – Need for low power
- Types of Power consumption
- Understanding CMOS and FinFET technology w.r.t types of power consumption
- Impact of technology shrinking on Vt
- Technology Scaling Vs Power
- Low power techniques
- Leakage power reduction techniques
- Dynamic power reduction techniques
- Understanding power architecture of SOC
- PMIC: Power Management Integrated Circuit
- PMU – Power management unit
- PMIC and SOC interfacing
- CPUSS – power architecture
- Verification goals in power aware simulations
- UPF History and commands
- UPF Design Data Flow
- Functional Intent Vs Power Intent
- UPF Concepts
- Power Intent
- Power Domain
- Retention register design
- Single control live slave
- Dual control Balloon
- Single control Balloon
- Retention Register relative layouts
- Storing the data during block power-down (Power Gating)
- Memory Retention methods
- Power Distribution
- Power states
- Sim states
- Verification of state retention logic in RTL
- UPF Power intent commands
- Steps for running power aware simulations
- UPF TB setup
- Memory controller architecture
- Memory controller low power verification setup
- Running low power simulations
- Low power simulations issues.
- Debugging low power issues
- Low power assertions and coverage
Course Overview
Power consumption is significant aspect of increasingly complex SOCs, which are typically used for portable systems. Low power design techniques helps identify the power behavior and minimize the power consumption. Both portable and non-portable systems, requires efficient power management techniques.
Student will learn SoC power domain architecture , in UPF how to define power intent – supply_port, supply_net, power cells like power switches, isolation cells, level shifters , retention cells, power state table and gating logic. Course is based on UPF3.1 LRM for defining the power intent in the UPF.
Course includes a hands on project covering the entire flow starting from understanding power architecture, developing UPF to capture the power intent, setting up the UPF based TB, running simulation and debugging the failures.
| Course | Power aware UPF verification |
|---|---|
| Duration | Live training : 3 weeks eLearning : 14 hours |
| Next Batch | |
| Schedule | Saturday, Sunday, 9AM to 1PM |
| Tool | Questasim |
| Mode of training | Live training for a minimum of 10 participants. eLearning mode. |
| Fee | INR 7K + GST |
- Course presentations for all topics
- Session notes
- Lab documents with detailed steps
- User guides
- DV engineers who wants to diversify their verification domain expertise.
- Understanding of SoC architectures, Verification of designs.
Experienced Trainer
- 10+ years of rich experience of working in Functional Verification domain across various mobile, networking, high speed peripheral domains.
- Experience of bringing up low power verification environment for a complex SOC.
Tab Content
