Syllabus
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Syllabus
Physical design basics course syllabus (Duration: 2.5 months)
- Specification
- RTL coding, lint checks
- RTL integration
- Connectivity checks
- Functional Verification
- Synthesis & STA
- Gate level simulations
- Power aware simulations
- Placement and Routing
- DFT
- Custom layout
- Post silicon validation
- Transistors in hardware design
- Significance of transistors in hardware design
- Logic gate implementation using BJT, CMOS
- MOSFET functionality
- Semiconductors
- What makes Semiconductor special element?
- Classification of solids into three types
- Conductor, Insulator, Semiconductor
- Energy bands in Solids
- Types of Semiconductors
- Intrinsic Semiconductors
- Extrinsic Semiconductors
- Types of Extrinsic Semiconductors
- N-type Extrinsic Semiconductor
- P-type Extrinsic Semiconductor
- Si, Ge – comparison
- Types of current in Semiconductors – Drift, Diffusion
- ion
- PN Junction dioda
- PN Junction – forward, reverse bias
- V-I Characteristics of PN Junction Diode
- Different types of Diode
- Applications of Diode
- BJT
- BJT
- BJT working principle?
- How BJT can be used for large scale manufacturing
- BJT fabrication steps
- Types of BJT?
- Why BJT is not used in for lower technology nodes?
- Issues with BJT?
- Advantages of BJT?
- NAND gate using BJT?
- Field Effect Transistor : FET
- What is Field Effect Transistor?
- Types of FET
- NMOS
- PMOS
- CMOS
- Fin
- NMOS
- NMOS
- What is NMOS?
- NMOS working principle?
- Different voltages, currents, their equations
- NMOS circuit representation
- How NMOS works like a switch
- How NMOS can be used for large scale manufacturing
- NMOS fabrication steps
- Types of NMOS?
- Why CMOS is used instead of NMOS?
- Issues with NMOS?
- Advantages of NMOS?
- NAND gate using NMOS?
- CMOS
- CMOS
- What is CMOS?
- CMOS working principle?
- Different voltages, currents, their equations
- CMOS circuit representation
- How CMOS works like a switch
- How CMOS can be used for large scale manufacturing
- CMOS fabrication steps
- Types of CMOS?
- Issues with CMOS?
- Advantages of CMOS?
- NAND gate using CMOS?
- CMOS second order effects?
- FinFET
- FinFET
- What is FinFET?
- FinFET working principle?
- Different voltages, currents, their equations
- CMOS circuit representation
- How CMOS works like a switch
- How FinFET can be used for large scale manufacturing
- FinFET fabrication steps
- Types of FinFET?
- Issues with FinFET?
- Advantages of FinFET?
- NAND gate using FinFET?
- FinFET second order effects?
- Layers of CMOS
- Depositing oxide layer
- Photolithography
- Masking
- Etching Layers
- Formation of nwell
- Self aligned gate fabrication process
- Diffusion to create n+ and P+ regions
- Metallization
- Combinational logic
- Number systems
- Radix conversions
- K-maps, min-terms, max terms
- Logic gates
- Realization of logic gates using mux’s and universal gates
- Compliments (1/2/9/10’s complement)
- Arithmetic operations using compliments
- Boolean expression minimization, Dmorgan theorems
- POS and SOP
- Conversion and realization
- Adders
- Half adder
- Full adder
- Subtractor
- Half subtractor
- Full subtractor
- Multiplexers
- Realizing bigger Mux’s using smaller Mux’s
- Implementing Adders and subtractors using Multiplexers
- Decoders and Encoders
- Implementing Decoders and Encoders using Mux and Demux
- Bigger Decoder/Encoder using smaller Decoder/Encoder
- Comparators
- Implementing multi bit Comparators using 1-bit Comparator
- Sequential logic
- Latch, Flipflop
- Latch, Flipflop using Gates or Mux’s
- Different types of FFs
- FF Truth table
- Excitation tables
- Realization of FF’s using other FF’s
- Applications of FF’s, Latches
- Counters
- Shift registers
- Synchronizers for clock domain crossing
- FSM’s
- Mealy, Moore FSM
- Different encoding styles
- Frequency dividers
- Frequency multiplication
- STA
- Setup time, Hold time, timing closure
- fixing setup time and hold time violations
- Launch flop, capture flop
- Introduction to majorly used keywords on PD flow
- VLSI Technology concepts
- Resistance, Capacitance, Inductance
- Parasitic capacitance
- L-C-R circuit analysis
- RC circuit significance with circuit delay
- Clock distribution concepts, skew
- Installing Linux platform in Windows
- Linux basics
- Linux versus Windows
- Linux Terminal
- File and Directory management
- Changing file permissions
- Absolute path and relative path
- Working with directories
- GVIM – major keyboard shortcuts
- Text display commands
- Root configuration files
- Environment variables
- Text processing commands
- grep, fgrep
- xargs
- SEd
- AWK
- Pipes and filters
- Connecting to server
- Process management
- LSF
- Ping
- FTP
- CTAGs
- File compress and extract
- Soft links
- Overview
- Env Setup
- Special Variables
- Data Types
- Variables
- Operators
- Decisions
- Loops
- Arrays, Strings, Lists, Dictionary
- History and Redoing of commands
- String Pattern Matching commands
Physical design main course syllabus (Duration: 4 months)
- Basics of Synthesis
- High Level Synthesis Flow
- Reading of Verilog RTL File
- Target and Link Libraries
- Resolving References with Link Libraries
- Reading hierarchical Designs
- Reading ddc design
- Analyse & Elaborate Commands
- Constraining and Compiling RTL
- Post Synthesis Output Data
- Constraining Register to Register Paths
- Constraining Inputs Paths
- Constraining Outputs Paths
- Virtual Clock
- Load Budgeting
- Default Path Groups
- Creating User-defined Path Groups
- Prioritizing Path Groups
- Timing Reports
- Analyzing Timing Reports
- Defining a Clock with additional options
- Input Delay with additional options
- Output Delay with additional options
- Pre-CTS versus Post CTS Clock Latencies
- Independent IO Latencies
- Output Delay with Network Latency
- Output Delay with Source Latency
- Different IO versus Internal Latencies
- IO Clock Latencies
- Handling Different IO Vs Internal Latencies
- Virtual External Clock Latencies
- Included External Clock Latencies
- Multiple Synchronous Clocks
- Multiple Clocks Input Delay
- Maximum Internal Input Delay
- Multiple Clock Output Delay
- Maximum Internal Output Delay
- Inter Clock Uncertainty
- Generated Clocks
- Mutual Exclusive Synchronous Clocks
- Logically Exclusive Clocks
- Multiple Clocks per Register
- Cross Talk Analysis
- Asynchronous Clocks
- Multi Cycle Paths and Constraints
- High Level Multi-Voltage Design Concepts
- Supplies and Power Domains
- Power Ports and Nets
- Level Shifters
- Power States and PS Table
- IC Compiler II Library Manager
- ICC Compiler II NDM Cell Library
- Cell Library Characteristics
- Library Manager Flow
- Tech Only NDM Library
- Technology-Only Library Flow
- Technology File
- Read TLU+ Files
- Tech Library Preparation
- Top Level, Sub-System Level and Block Level Design Setup
- Set up initial Design Implementation
- Loading Netlist from Synthesis
- Setting Path to dotlibs, LEFs, DEFs (if needed), Technology Files, SDC files
- Flow Setup and Design Setup
- Loop-back to Synthesis for Correlation issues correction
- Running placement
- Defining placement strategies
- In Place Optimization
- Hierarchical Placement
- Relative Placement
- Congestion analysis and reduction
- Macro placement changes to reduce congestion
- Standard Cell Placement Constraints
- Halo creation for instances
- Congestion Analysis with Standard Cell placement
- Local Congestion Reduction
- Density Screen and Placement Blockage for Standard Cells
- Congestion Aware Placement
- Re-Check Macro Placement for better Congestion relief
- Create Balanced Buffer Trees for High Fanout Net
- Defining Power Structure
- Logical Power/Ground Connections
- Setting Power Network Constraints
- Create and Analyze Power Structure
- Change Power Constraints and Re-Createto meet IR requirements
- Power Ground Pin connection and create Power Rails
- Power Network Checks for IR and Resistance
- Placement Blockage for Power Network
- Incremental Placement
- Re-Order Scan connectivity within Chain
- Re-Partition Scan connectivity across Chains
- SCANDEF file based Scan Chain Re-Ordering
- Initial Floorplanning settings
- Define Pad Instances (Physical Cells)
- Pad Instance co-ordinates
- Start Floorplaning
- Core Die Size setting
- Floorplanning of Pad Instances
- Pad Filler Insertion
- Define Pad Ring Power Grid
- Macro Instance constraints
- Macro Instance Array creation
- Macro Instance Orientation
- Anchor based and Relative Placement of Macro Instances
- Macro Instance-Channel settings
- Macro Instance placement – Manual
- Congestion probability around Macro Instances
- Defining Placement Blockages
- Congestion checks for Overflow again
- RC extraction for Net Parasitics
- Check Timing for Max Analysis
- Run Timing/Congestion aware Placement
- Logic Re-Structuring for Placement and Timing
- Check Pre-CTS timing based on Global Routing and Detailed Placement
- Setting Clock Constraints such as Target Skew Target Insertion Delay
- Clock Root Attributes as Stop, Float and Exclude Pins
- Building for Generated and Gated Clocks
- Don’t Touch attribute on existing Clock Tree structure
- Defining Clock Buffers and Inverters.
- Set Clock Tree Timing DRCs.
- Non-Default Clock Routing rules setting
- Perform Clock Tree Synthesis and Clock Tree Optimization
- Reduce Hold Violations in Data paths and Scan Paths
- Clock Tree Building/Optimization for Multiple modes and Multiple PVT corners
- Synchronous Clock Balancing
- Cross-Clock Delay Balancing
- Logical Hierarchy aware CTS
- Max and Min Analysis and subsequent Optimization
- Fixing Violations
- CTS Optimization across other modes and PVT corners (MMMC)
- Skew and Insertion Delay checks
- Checking Crosstalk on Clock Network
- Pre-Route check points
- Routing fundamentals
- Global Route
- Detail Routing
- Track Assignment and Route
- Refining Detailed Route
- Over the Macro routing
- Non-Preferred Routing direction
- Clock Net Routing
- Initial Data path routing
- Redundant VIA insertion setting
- Post Detailed Route Optimization
- Fixing DRC Violations
- Post Detailed Route Delay Calculation Algorithms
- Crosstalk Delay and Noise Analysis and Fix
- Check Leakage Power Dissipation
- VT Cell swap for power and timing trade-off
- Analyzing Dynamic Power Dissipation based on GAF, SAIF, VCD
- Reduce Dynamic power
- Meet Total Power target
- Functional ECO
- Timing ECO
- Metal Only ECO using Spare Cells for base frozen designs
- Projects covering detailed flow from Input files, floorplan, power planning, placement, CTS, Routing, SPEF extraction, STA, and Physical verification.
- One project completely guided by the trainer
- Other project done by student with trainer guidance
- Project based on multi voltage domain.
- Antenna Rules and Fixes
- Critical Area Analysis
- Wire Spreading and widening
- Setting minimum metal jog length
- Filler Cell Insertion
- Metal Fill
- Timing Checks after Metal Fill
- Parasitic Extraction for SignOff timing analysis
- Export Netlist
- Export GDSII
- Facing interviews effectively
- Industry work culture
- Group discussions
Course Overview
Course Overview
Physical Design Training is a 6.5 months course focused on all the aspects of VLSI starting from Device fundamentals, IC fabrication, timing concepts. advanced digital design, Linux OS, TCL scripting and entire VLSI backend flow.
Course is structured to enable students gain in-depth knowledge of all aspects of Physical design flow from Netlist to GDSII including Floor planning, Placement, power planning, scan chain reordering, global routing, clock tree synthesis, power analysis and ECO.
Course also includes multiple hands on projects using Synopsys Implementation flow(DC, ICC II, Star RC, PT, ICV).
Physical Design training program is well illustrated and supported with real-time examples from the industry.
Floor planning, Placement and Routing, Clock Tree Synthesis, Final Routing and Timing Closure forms the core of the Physical Design Training program structure.
Thorough and micro level wide understanding of the concepts across all the Physical Design flow would be the key highlight of this program. Complete Theory Sessions and complementing Lab Sessions with projects (Block level and Full chip level) from Netlist to GDSII, guided well by expert trainer are offered for every candidate of this Physical Design Training program.
Physical Design Training also includes 40+ assignments covering all aspects physical design implementation flow including practical aspects. Assignments are detailed and well structured to cover all the aspects of Physical Design. These assignments will solved as part of course lectures.
VLSIGuru Institute is setup in 2012, helped 10000+ students find right career opportunities. VLSIGuru offers affordable Physical Design Training in Bangalore. Online Physical Design Training is offered for students based out of Bangalore.
Projects
Schedule
Course is offered in 2 modes:
- Full week course (for freshers)
- 9AM to 1PM on 6 days/week (Friday is break)
- Weekends only course (for working professionals)
- 9AM to 5:30PM on both Saturday & Sunday
- Session timings might differ for students from US and other times zones.
- 9AM to 5:30PM on both Saturday & Sunday
| Course | Physical Design Training |
|---|---|
| Duration | 6.5 months |
| Course start date | 24/November |
| Schedule | |
| Freshers | 6 days/week 9:30AM – 1:30PM IST |
| Working professionals | Saturday & Sunday Theory session : 9:30AM to 1:30PM Lab session : 2:30PM to 6PM (different timings for students from US and Canada) |
| New batch starts | Every 6 Weeks |
| Tools | Synopsys ICC II, Primetime, StarRC, Design Compiler, ICV |
| Mode of training | Classroom training Live online training eLearning mode with dedicated mentor for doubt clarifications |
| Fee | Live training : 63K + GST eLearning : 45K + GST |
| Tool Access | 24×7 Tool access for complete course duration |
| Certificate | Issued based on 50% assignment completion as criteria |
| Batch Size | 25 |
| Assignments | 20 |
| Placement support | 100% support till student gets a job. |
| Trainer | Experienced trainers working on latest technologies in top MNCs. |
Demo
FAQs
- Course presentations for all topics
- Session notes
- Lab documents with detailed steps
- User guides
- Yes, Course fee also includes support for doubt clarification sessions even after course completion
- You have option to mail you queries
- Option to meet in person to clarify doubts
- Most of the times, reasoning for any institute to charge higher fee(excess of 1 lakh) is tool cost is high. It is not true.
- VLSIGuru believes in creating an educational model that is affordable and sustainable in the long run. We have been running successfully since we started training in 2012 with 3500+ students trained so far. We take pride in the fact that, it is VLSIGuru which made other institutes also to offer courses in 30K to 50K range, otherwise it used to be much higher.
- Institute owns the office facility, hence we avoid rental expense. Keeping it aside, we also find it difficult to comprehend why course fee should be in excess of 1 Lakh.
- Good understanding VLSI Technology basics(CMOS, FinFET, etc)
- Digital design concepts
- Each session of course is recorded, missed session videos will be shared
- Yes, You will have option to view the recorded videos of course for the sessions missed
- You will have option to repeat the course any time in next 1 year
Trainer
Multiple Trainer
- Multiple trainers each with 15+ years of rich experience of working on complex SOC backend flow in various technology from 45nm to 7nm
- Multiple trainers with exposure to all the industry standard flow starting from Synopsys and Magma
Certificate
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- 1-1 Dedicated Mentor Support
- 24/7 Tool Access
- Multiple mock interviews
- Industry Standard Projects
- Support with resume update