Course Overview

Synthesis and STA Training is a 4 months course, provides the participants with in depth exposure to both Synthesis and complete Timing SignOff strategies for successful and confident Tape-Out of the Design to the Semiconductor Fabrication House.

STA Training:

Timing is the heart beat of any chip, thorough understanding of timing concepts, development of Timing constraints are given through this STA Training especially when it comes to Ultra Deep Sub-Micron Technologies such as 28nm to 5nm.

There are multiple parameters that decide how the timing of a chip would be functioning like Transition times of Clock phases and Data Path signals, Process and Voltage and Temperature (PVT) variations, Crosstalk noise affecting functionality of the chip, Crosstalk Delay affecting timing of the chip, which will be covered in greater detail in this STA Training. Other topics such as Advanced OCV, requirement of Clock path tweaking to meet desired frequency of the Chip will be discussed extensively in this STA Training. Pessimism inclusion when design is taped-out has been a norm to avoid any Silicon surprises but for higher frequency Designs on lower technology nodes, pessimism beyond a limit could be an over-do in which case pessimism-Removal is done through Path-Based Analysis rather than Graph based Analysis. This topic is covered with fine clarity in this STA Training. Above all, the fundamental part of setup and hold time fixing covering the above points are the key aspects of this STA Training.

Candidates will get access to tool both at institute and has option to connect to servers from home using Secure VPN to work on two Sign Off projects hands on. Fixing of timing violations based on Sign-Off analysis for Multi Mode Multi Corner though ECOs would be across the breadth of this STA Training.

Objective of this STA training is to shape graduating Bachelor’s and Master’s degree students as well as Physical Design Engineers explore opportunities in Block Level as well as Full Chip STA.

Synthesis Training:

Synthesis training includes all the aspects starting from HDL modelling, Synthesis flow, Constraints, analysing and debugging the results, optimization techniques, report generation and hands on projects to understand the Synthesis complete flow.

Below are the STA Training topics.

SignOff STA Training topics :

Fundamental Setup and Hold Timing Checks

Timing Arcs across Design Instances

Stage Delay covering Cell Delay and Net Delay

Asynchronous Flop, recovery and removal checks

Cross Clock Timing Analysis

Interface Timing Analysis (between reg and IO)

Clock group based timing analysis

Crosstalk Delay and Crosstalk Noise

Advanced On Chip Variation, CPPR

Multi-Mode Multi-Corner timing analysis

Graph Based and Path based analysis

Timing DRC – Transition, Capacitance, Fanout fixes.

Clock path ECO and Data path ECO

Constraint Development specifically Interface timing

Synthesis Training covers the aspect of converting the design in form of RTL into Technology mapped netlist. Synthesis is an algorithm intensive task consisting of many stages within it requiring various inputs in order to produce a functionally correct netlist. The main part of Synthesis Training consists of reading in the design, converting RTL to Boolean equations through elaboration, then converting the Boolean equations to Generic Mapped Cells and then technology mapped cells from library, setting constraints, optimizing the design, analyzing the results and saving the design database for Placement and Routing stage to take on. Candidates who are interested in exploring opportunities in Synthesis and Front-end STA can undergo this in-depth Synthesis training to get good understanding of RTL constructs, Gate level Netlist, Constraint Development, Latch based designs, pipe lining and re-timing, basic Scan stitching, Setup timing closure, Topography based logic re-structuring, Wire Load Models, Logical Equivalence Checks. Hierarchical Synthesis is another key feature covered in this Synthesis Training Cadence Implementation Suite for Synthesis (as RTL Compiler / Genus) would be used in this Synthesis Training program. Candidates would get hands on work on two full designs.

Synthesis Training Topic covered.

Introduction to synthesis.

Reading RTL in HDL form, dotlibs, SDC

Different types of RTL constructs

Analyzing dotlib files

Elaboration and Generic Synthesis

Understanding DesignWare components and Logical Operators

Clock gating insertion for reducing Dynamic power post CTS

Creating list of dont_touch and dont_use cells

Technology mapped Synthesis and optimization

Scan Insertion techniques

Checking Design for number of instances, area estimate

Check clock reaching clock pins of flops, unclocked flops

Time borrowing concepts for latch based paths

Leakage variants of standard cells LVT, RVT, HVT

Constraints on logical hierarchy boundaries

Setting Max Transition, Max Capacitance, Max Fanout

Push down and pull up timing constraints

Master clocks and generated clocks in design

Estimating uncertainty values, input and output delays in SDC

False path, Multi cycle path exceptions.

Disabling timing loops in design

Logical Equivalence Checking fundamentals (Top level and Hierarchical)

Hand off database to PnR